DE3378869D1 - A method of forming electrodes and wiring strips on a semiconductor device - Google Patents

A method of forming electrodes and wiring strips on a semiconductor device

Info

Publication number
DE3378869D1
DE3378869D1 DE8383101880T DE3378869T DE3378869D1 DE 3378869 D1 DE3378869 D1 DE 3378869D1 DE 8383101880 T DE8383101880 T DE 8383101880T DE 3378869 T DE3378869 T DE 3378869T DE 3378869 D1 DE3378869 D1 DE 3378869D1
Authority
DE
Germany
Prior art keywords
semiconductor device
forming electrodes
wiring strips
strips
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383101880T
Other languages
German (de)
English (en)
Inventor
Yoshitaka Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3378869D1 publication Critical patent/DE3378869D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8383101880T 1982-03-16 1983-02-25 A method of forming electrodes and wiring strips on a semiconductor device Expired DE3378869D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57041331A JPS58158972A (ja) 1982-03-16 1982-03-16 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3378869D1 true DE3378869D1 (en) 1989-02-09

Family

ID=12605531

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383101880T Expired DE3378869D1 (en) 1982-03-16 1983-02-25 A method of forming electrodes and wiring strips on a semiconductor device

Country Status (4)

Country Link
US (1) US4521448A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0088922B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS58158972A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3378869D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074682A (ja) * 1983-09-30 1985-04-26 Toshiba Corp 半導体装置の製造方法
EP0159601A3 (de) * 1984-04-10 1987-08-19 Hartwig Wolfgang Prof.Dr. Thim Logik-Schaltungsanordnung mit dazu angepasst ausgebildeten Feldeffekt-Transistoren
JPH0760864B2 (ja) * 1984-07-13 1995-06-28 株式会社日立製作所 半導体集積回路装置
US4642878A (en) * 1984-08-28 1987-02-17 Kabushiki Kaisha Toshiba Method of making MOS device by sequentially depositing an oxidizable layer and a masking second layer over gated device regions
JPS61135149A (ja) * 1984-12-06 1986-06-23 Toshiba Corp Ｍｏｓ型集積回路
US5227319A (en) * 1985-02-08 1993-07-13 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JPS61287159A (ja) * 1985-06-13 1986-12-17 Oki Electric Ind Co Ltd Ｂｉ−ＣＭＯＳ半導体ＩＣ装置の製造方法
US4760433A (en) * 1986-01-31 1988-07-26 Harris Corporation ESD protection transistors
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US5256583A (en) * 1986-03-21 1993-10-26 Advanced Power Technology, Inc. Mask surrogate semiconductor process with polysilicon gate protection
JPS62252891A (ja) * 1986-04-25 1987-11-04 Sumitomo Heavy Ind Ltd 向流式浮動プレ−ト型熱交換器
US4794565A (en) * 1986-09-15 1988-12-27 The Regents Of The University Of California Electrically programmable memory device employing source side injection
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
JPH01173756A (ja) * 1987-12-28 1989-07-10 Toshiba Corp 半導体装置の製造方法
GB2214349B (en) * 1988-01-19 1991-06-26 Standard Microsyst Smc Process for fabricating mos devices
JP2705106B2 (ja) * 1988-05-25 1998-01-26 セイコーエプソン株式会社 半導体装置の製造方法
FR2634318B1 (fr) * 1988-07-13 1992-02-21 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire integree
US4948745A (en) * 1989-05-22 1990-08-14 Motorola, Inc. Process for elevated source/drain field effect structure
US5013675A (en) * 1989-05-23 1991-05-07 Advanced Micro Devices, Inc. Method of forming and removing polysilicon lightly doped drain spacers
US5212105A (en) * 1989-05-24 1993-05-18 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device manufactured thereby
JP2995838B2 (ja) * 1990-01-11 1999-12-27 セイコーエプソン株式会社 Ｍｉｓ型半導体装置及びその製造方法
US5013398A (en) * 1990-05-29 1991-05-07 Micron Technology, Inc. Anisotropic etch method for a sandwich structure
US5496750A (en) * 1994-09-19 1996-03-05 Texas Instruments Incorporated Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition
US20020197838A1 (en) * 1996-01-16 2002-12-26 Sailesh Chittipeddi Transistor fabrication method
US6225174B1 (en) * 1996-06-13 2001-05-01 Micron Technology, Inc. Method for forming a spacer using photosensitive material
US7365369B2 (en) 1997-06-11 2008-04-29 Nichia Corporation Nitride semiconductor device
US6051487A (en) * 1997-12-18 2000-04-18 Advanced Micro Devices, Inc. Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode
US6281078B1 (en) 1997-12-18 2001-08-28 Advanced Micro Devices, Inc. Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices
US5994239A (en) * 1997-12-18 1999-11-30 Advanced Micro Devices, Inc. Manufacturing process to eliminate polystringers in high density nand-type flash memory devices
US6063668A (en) * 1997-12-18 2000-05-16 Advanced Micro Devices, Inc. Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices
US6448615B1 (en) 1998-02-26 2002-09-10 Micron Technology, Inc. Methods, structures, and circuits for transistors with gate-to-body capacitive coupling
US6104066A (en) 1998-03-30 2000-08-15 Micron Technology, Inc. Circuit and method for low voltage, voltage sense amplifier
JP3770014B2 (ja) 1999-02-09 2006-04-26 日亜化学工業株式会社 窒化物半導体素子
DE60043536D1 (de) 1999-03-04 2010-01-28 Nichia Corp Nitridhalbleiterlaserelement
US6197673B1 (en) * 1999-06-08 2001-03-06 United Semiconductor Corp. Method of fabricating passivation of gate electrode
JP4468609B2 (ja) * 2001-05-21 2010-05-26 株式会社ルネサステクノロジ 半導体装置
TWI362769B (en) 2008-05-09 2012-04-21 Univ Nat Chiao Tung Light emitting device and fabrication method therefor
US9236243B2 (en) 2014-01-09 2016-01-12 Stmicroelectronics Pte Ltd Method for making semiconductor devices including reactant treatment of residual surface portion
US11063117B2 (en) * 2017-04-20 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having carrier-trapping layers with different grain sizes

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4354896A (en) * 1980-08-05 1982-10-19 Texas Instruments Incorporated Formation of submicron substrate element

Also Published As

Publication number Publication date
JPH0479133B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-12-15
EP0088922A2 (en) 1983-09-21
EP0088922A3 (en) 1985-07-03
US4521448A (en) 1985-06-04
JPS58158972A (ja) 1983-09-21
EP0088922B1 (en) 1989-01-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee