DE3328389A1 - Separately constructed serial tetrad adder/subtracter in BCD 8421 code - Google Patents

Abstract

Published without abstract.

Description

Serial tetrad-adder-subthread "] ' - · ■■■ '■ ·;. ■ · in BGD-a421 code ·. “. "'' ··· '■' ^r '- · - ■ · -' · - ■" ■ '■; in separate execution; .-, ..- .. ■. /,

. - The subject of the invention is the two-part training of the ν serial tetrad-adding-subtracting after the main. .Patent application. The serial tetrad-adding-subtracting mechanism · na.ch the subject of the invention exists? Consequently; from a serial tetrad adding unit and a serial tetrad subtracting unit. r: /: * ·. · .. '., · ■ ·. ,

In Figure 1 is the corresponding serial tetrad adder; 10 and in FIG. 2 the corresponding serial tetrad subtracter 20. In FIG. 3 the tetrad adder A is shown and in FIG. 4 the corresponding tetrad subtracter 2. In FIG. 5 is the BGD-BGD -plus-6-Unicode circuit 7 shown ', which four-digit BCD numbers in

• four-digit BGD-plus-6 numbers recoded .-.,.

The serial tetrad adder 10 of this two-part

• serial tetrad-adder-subtracter consists of the

'Special tetrad adder · 1 and the carry memory 4 and' · '■■ the encoding circuit 7 and the associated lines. The special tetrad adder 1, which is shown in Figure 3 as a circuit, consists of the full adders 11 to 14 and the full subtractor 26 and the half subtractor and the remainder circuit 27 and the negation circuit 9 and the associated lines . The recoding circuit 7 (FIG. 5), which recodes four-digit BCD numbers into four-digit BCD-plus-6 numbers, consists of the input part 7 a and the output part 7 b. Either the first or second summand can be entered at inputs E; the summand which is not used for. the inputs E is provided. The outputs E are the result outputs, which have BCD-coded the potential series of the GOPY additions resultant number when the inputs S and jL - each have a line summand SC "-coded.

The associated tetrad subtractor 20 of this ^ two double rope serial tetrad adder-subtractor is 4 · and "the associated lines from dam tetrad subtractor 2 and dam transfer memory. The tetrad subtractor 2, which in Figure 4 as S The circuit shown consists of the full subtractors * 21 to 24 and the full subtractor 26 and the half subtractor 25 and the remainder circuit 27, which is the same for addition and subtraction. The inputs E are the minuend inputs and the inputs F are the subtra-.hend inputs. The outputs ^ are the result outputs.

The mode of operation of the serial tetrad adder 10 of this two-part tetrad adder-subtractor results from adding as follows: If the first-line addend of the first addend is BOD-coded at the Ε-inputs and the first line addend des second addend also only ECD-coded at the F inputs, the first line addend of the first addend is BOD-coded at the corresponding inputs of the tetrad adder 1 and the first line addend of the second addend BCD-plus-6 -coded at the other inputs of the tetrad adder 1. If the carry output y has no Η potential, this line sum is carry-free and the line i has Η potential -26-25) at the same time the. Jforecture number LHHL (6) is subtracted, as a result of which the potential series of the addition result number is present in BOD-coded form at the outputs K. If the output γ has Η potential here, this line sum has a carry and thus the line i has L potential. This means that the correction circuit (27-26-25) does not subtract the correction number LHHL (6) and thus the. The fact that the result status was already reduced by the number 16 instead of just by the number 10 due to the tetrad carryover is also only BOD-coded at the outputs K, the potential series of the addition result number minus the number 10 before. If there is also a tetrad carryover at the tetrad carry input χ,. this is added as the number 1 at the same time.

How the serial Deuradsn-Sub'tiranierweVAs 20 ° works this two-part Tecraden-adding-subtracting mechanism results when subtracting as follows: If the first line minuend of the minuend. is applied to the E inputs and the first line subtrahend of the subtrahend at the F inputs, both four-digit BCD numbers are BCD-coded at the corresponding inputs of the tetrad subtracter 2. If the carry output y has no Η potential, this subtraction result number (line difference) is carry-free and the line m has L potential. Thus, the correction circuit (27-26-25) receives the correction number LHHL (6) not subtracted because this subtraction is not necessary in this case. This means that the outputs K are BCD-coded the potential series of the subtraction result number. If the output y has Η potential, this has line sum a carry and thus the line m H potential. This is done by the correction circuit C27-26-25) at the same time the correction number LHHL (6) is subtracted and thus the circumstance takes into account that the result status increased by the number 16 instead of only due to the tetrad carryover around the number 10. The BCD-coded potential series of the subtraction result number is at the outputs K plus the number 10. If this also occurs at the carry input χ a carry is pending, this is subtracted as number 1 at the same time.

^ - '* "<,. 1328389

The mode of operation results in the case that the correction durciL subtraction of the correction number LHEL (6) is done as follows:

+ 5

5 + 9 = 4 and plus carry

LHLL + HLLH

LHHH

+

HHLH

-LHHL -

L. H L. H 5 + H H H H + 15 H L H L. L. 20 -η - L L. L. L. L. H L. L. - 4th - 0 4th

8-3

2-4 = 8 and minus carry-over

H L. L. L. 8th H L. L. H L. L. L. H H - 3 - L H L. L. L. H L. H 5 H H H L. L. L. L. L. - 0 - L H H L. L. H L. H 5 H L. L. L.

- 2

• 14 - 6

In the case that the correction is made by adding the number HLHL (10) nr / , the Wirtaingsweise results as follows: / Λ \)

L. H L. L. + 9 + H L. L. H 1 3 H H L. H + 1 0 + H L. H L. 2 3 L. H H H

H L. L. L. 8th L. L. H H - 3 L. H L. H 5 L. L. L. L. + 0 L. H L. H 5

9 = 4 and plus carry

L. H L. H 5 i H H H H + 15 ' - »- H- L. H L. L. 20 - + 0 L. L. L. L. H- L. H L. L.

8-3 = 5 2 - 4 · ■ 8 and minus carry

L. L. H L. 2 - L H L. L. - H- H H H H L. - 2 - + H L. H L. H L. L. L. - »- 14- + 10 24-

Correction tetrad carryovers that arise here are therefore invalid and are therefore not processed.

-1-

- Blank page

Claims (10)

Q) Serial electronic tetrad-adder-subtracter in the BCD-8421 code, which is "a tetrad adder-subtracter- • it has which can be switched from addition to subtraction and which can be switched from subtraction to addition and its tetrad adder-subtracter works in the following way when adding with the input level raised that the line summands of one of the two summands are increased by the number LHHL (6) or that the line Summands of both summands in pairs are increased by the number LHHL (6) and only when added without tetrad carryover and with subtraction with tetrad carryover, a correction of the result number is required is, characterized in that this serial tetrad-adding-subtracting mechanism is designed in two parts and thus consists of a serial tetrad adding unit (10) and a serial tetrad subtracting unit (20). 2.) Serial electronic tetrad adder-subtracter according to claim 1, characterized in that the serial tetrad adder (10) from a tetrad adder (1) - and a tetrad carry memory (4) and an input -Urne odierschaltung ( 7) and the other parts and that the tetrad adder (1) consists of a main circuit (41) and a correction circuit (42) and an additional negation circuit (9) and that the input recoding circuit (7) is a recoding circuit which four-digit BCD numbers are recoded into four-digit BCB-plus-6 numbers and that the correction circuit (42) subtracts the number LHHL (6) when adding without tetrad carryover. 3) Serial electronic tetrad-adder-subtracter according to claim 1 and 2, characterized in that the serial tetrad subtracter (20) from a tetrad subtractor (2) and a tetrad carry memory (4) and the other parts and that the tetrad subtracter (2) consists of a main circuit (43) and a correction circuit (42) and that the correction circuit: (42) with subtraction with tetrad carryover the- ) - - COPY Number LHKL (6) subtracted. 4) Serial electronic tetrad-adder-subtracter after. Claim. 1 bi3 3, characterized in that-the ■ Main circuit (41) of the tetrad adder (1) from 4 ■ *. Full adders (11 to 14) and that the correction circuit (42) of this tetrad adder (1) from the '' 'half subtractor (25) and the full subtractor (26) and "" - ■ • the äest circuit (27) consists of ... ·, ..., 5) Serial electronic tetrad-adder-subtracter. ■ according to claim 1 to 4, characterized in that the •. .Main circuit (43) of the tetrad subtracter (2) from FIG • Full subtractors (21 to 24) and that the correction circuit (42) of this tetrad subtracter (2) from the half subtracter (25) and the full subtracter (26) and the remainder circuit (27). 6) Serial electronic tetrad-adder-subtracter according to claim I. to 5i, characterized in that at the tetrad adder (1) and the tetrad subtractor (2) as a special version, a different correction circuit instead of the correction circuit (42) is used, which does not subtract the number LHHL (6), but the number HLHL (10) is added and that the resulting correction tetrad carryover is not processed will. 7) serial electronic tetrad-adder-subtracter according to claim 1 to 3 or 1 to 5 or 1 to 6, characterized characterized that its part 10 (serial tetrad adder) is used in conjunction with another subtracter '. 8) Serial electronic tetrad-adder-subtracter according to claim 1 to 3 or 1 to 5 or 1 to 6, characterized in that its part 20 (serial tetrad subtracter) is used in conjunction with another adder. 9) Serial electronic tetrad adder, characterized in, that it consists of a tetrad adder (1) and a tetrad carry memory (4) and an input • Coding circuit (7) and the other parts exist and - That the tetrad adder (1) consists of a main circuit (41) and a correction circuit (42) and an additional Negating circuit (9) and that the input .; Recoding circuit (7) is a recoding circuit which ■ four-digit BCD numbers in four-digit BGD plus 6 numbers •. recoded and that the correction circuit (42) upon addition without tetrad carryover the number LHHL (6) is subtracted or that in place of the correction circuit (42) another correction circuit is arranged which does not have the number·LHHL (6) is subtracted, but the number .HLHL (10) is added and the resulting correction tetrad carryover is not processed. 10) Serial electronic tetrad subtracter, characterized in that it consists of a tetrad subtractor (2) and a tetrad transfer memory (4) and the other parts and that the tetrad subtracter (2) consists of a main circuit (43) and a correction circuit (42) and that the correction circuit (42) in subtraction with tetrad carry-over the number LHHL (6) is subtracted or that instead of the correction circuit (42) another ' Correction circuit is arranged, which does not subtract the number LHHL (6), but adds the number HLHL (10) . and that the resulting correction tetrad carryover ■ is not processed.