DE3278602D1 - Semiconductor device with fuse - Google Patents

Semiconductor device with fuse

Info

Publication number
DE3278602D1
DE3278602D1 DE8282306892T DE3278602T DE3278602D1 DE 3278602 D1 DE3278602 D1 DE 3278602D1 DE 8282306892 T DE8282306892 T DE 8282306892T DE 3278602 T DE3278602 T DE 3278602T DE 3278602 D1 DE3278602 D1 DE 3278602D1
Authority
DE
Germany
Prior art keywords
fuse
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282306892T
Other languages
German (de)
English (en)
Inventor
Hajime Kamioka
Mikio Takagi
Noriaki Sato
Motoo Nakano
Takashi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3278602D1 publication Critical patent/DE3278602D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
DE8282306892T 1981-12-28 1982-12-23 Semiconductor device with fuse Expired DE3278602D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56209766A JPS58115692A (ja) 1981-12-28 1981-12-28 プログラマブル・リードオンリメモリのヒューズ切断方法

Publications (1)

Publication Number Publication Date
DE3278602D1 true DE3278602D1 (en) 1988-07-07

Family

ID=16578260

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282306892T Expired DE3278602D1 (en) 1981-12-28 1982-12-23 Semiconductor device with fuse

Country Status (4)

Country Link
US (1) US4503315A (enExample)
EP (1) EP0083211B1 (enExample)
JP (1) JPS58115692A (enExample)
DE (1) DE3278602D1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59125640A (ja) * 1982-12-28 1984-07-20 Fujitsu Ltd 半導体装置の製造方法
US4720470A (en) * 1983-12-15 1988-01-19 Laserpath Corporation Method of making electrical circuitry
JPS60176250A (ja) * 1984-02-23 1985-09-10 Toshiba Corp 半導体装置の製造方法
US5008729A (en) * 1984-06-18 1991-04-16 Texas Instruments Incorporated Laser programming of semiconductor devices using diode make-link structure
JPS6122650A (ja) * 1984-07-11 1986-01-31 Hitachi Ltd 欠陥救済方法および装置
JPH0719842B2 (ja) * 1985-05-23 1995-03-06 三菱電機株式会社 半導体装置の冗長回路
US4681778A (en) * 1985-11-14 1987-07-21 Optical Materials, Inc. Method and apparatus for making electrical connections utilizing a dielectric-like metal film
JPH06105764B2 (ja) * 1986-06-20 1994-12-21 株式会社東芝 ヒユ−ズ内蔵型半導体装置
JPS6334952A (ja) * 1986-07-29 1988-02-15 Nec Corp 半導体装置内の回路選択用ヒユ−ズ
JPS63140550A (ja) * 1986-12-01 1988-06-13 Mitsubishi Electric Corp 冗長回路用電気ヒユ−ズ
US4764485A (en) * 1987-01-05 1988-08-16 General Electric Company Method for producing via holes in polymer dielectrics
US4872140A (en) * 1987-05-19 1989-10-03 Gazelle Microcircuits, Inc. Laser programmable memory array
JPS645033A (en) * 1987-06-26 1989-01-10 Nec Corp Semiconductor device
US4853758A (en) * 1987-08-12 1989-08-01 American Telephone And Telegraph Company, At&T Bell Laboratories Laser-blown links
JP2508247B2 (ja) * 1989-03-20 1996-06-19 三菱電機株式会社 マスクｒｏｍの製造方法
US5982268A (en) * 1998-03-31 1999-11-09 Uchihashi Estec Co., Ltd Thin type fuses
US6633055B2 (en) 1999-04-30 2003-10-14 International Business Machines Corporation Electronic fuse structure and method of manufacturing
DE19924153B4 (de) * 1999-05-26 2006-02-09 Infineon Technologies Ag Schaltungsanordnung zur Reparatur eines Halbleiterspeichers
US6166421A (en) * 1999-08-18 2000-12-26 National Semiconductor Corporation Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment
KR100408137B1 (ko) * 2001-11-26 2003-12-06 학교법인 성균관대학 중성빔을 이용한 층대층 식각장치 및 식각방법
JP4473715B2 (ja) * 2004-11-29 2010-06-02 富士通株式会社 積層体切断方法及び積層体
US7477130B2 (en) * 2005-01-28 2009-01-13 Littelfuse, Inc. Dual fuse link thin film fuse
JP4975669B2 (ja) * 2008-03-25 2012-07-11 株式会社東芝 赤外線検出器およびこの赤外線検出器を備えた固体撮像素子
JP2017045839A (ja) * 2015-08-26 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564354A (en) * 1968-12-11 1971-02-16 Signetics Corp Semiconductor structure with fusible link and method
DE2625089A1 (de) * 1976-06-04 1977-12-15 Bosch Gmbh Robert Anordnung zum auftrennen von leiterbahnen auf integrierten schaltkreisen
US4240094A (en) * 1978-03-20 1980-12-16 Harris Corporation Laser-configured logic array
US4209894A (en) * 1978-04-27 1980-07-01 Texas Instruments Incorporated Fusible-link semiconductor memory

Also Published As

Publication number Publication date
EP0083211A3 (en) 1985-04-17
EP0083211A2 (en) 1983-07-06
EP0083211B1 (en) 1988-06-01
JPH0379871B2 (enExample) 1991-12-20
US4503315A (en) 1985-03-05
JPS58115692A (ja) 1983-07-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee