DE3277158D1 - Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers - Google Patents

Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers

Info

Publication number
DE3277158D1
DE3277158D1 DE8282304745T DE3277158T DE3277158D1 DE 3277158 D1 DE3277158 D1 DE 3277158D1 DE 8282304745 T DE8282304745 T DE 8282304745T DE 3277158 T DE3277158 T DE 3277158T DE 3277158 D1 DE3277158 D1 DE 3277158D1
Authority
DE
Germany
Prior art keywords
integrated circuit
semiconductor
interconnecting layers
semiconductor substrate
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282304745T
Other languages
German (de)
English (en)
Inventor
Tetsu Tanizawa
Yoshiharu Mitono
Hitoshi Omichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3277158D1 publication Critical patent/DE3277158D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/901—Masterslice integrated circuits comprising bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8282304745T 1981-09-10 1982-09-09 Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers Expired DE3277158D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56142941A JPS5844742A (ja) 1981-09-10 1981-09-10 半導体集積回路装置

Publications (1)

Publication Number Publication Date
DE3277158D1 true DE3277158D1 (en) 1987-10-08

Family

ID=15327203

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282304745T Expired DE3277158D1 (en) 1981-09-10 1982-09-09 Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers

Country Status (3)

Country Link
EP (1) EP0074804B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5844742A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3277158D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59139646A (ja) * 1983-01-31 1984-08-10 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
JPH0669142B2 (ja) * 1983-04-15 1994-08-31 株式会社日立製作所 半導体集積回路装置
JPH0817227B2 (ja) * 1987-04-30 1996-02-21 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 個性化可能な半導体チップ
KR920005863B1 (ko) * 1988-08-12 1992-07-23 산요덴끼 가부시끼가이샤 반도체 집적회로
JPH02194173A (ja) * 1989-01-20 1990-07-31 Chugai Ro Co Ltd スパッタリング装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983619A (en) * 1968-01-26 1976-10-05 Hitachi, Ltd. Large scale integrated circuit array of unit cells and method of manufacturing same
JPS55163859A (en) * 1979-06-07 1980-12-20 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
EP0074804A2 (en) 1983-03-23
JPS643056B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-01-19
EP0074804A3 (en) 1984-11-28
JPS5844742A (ja) 1983-03-15
EP0074804B1 (en) 1987-09-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee