DE3264586D1 - Integrated process for manufacturing logical circuits comprising at least one field effect transistor having a low threshold voltage and a saturation resistor, and logical circuit made by that process - Google Patents

Integrated process for manufacturing logical circuits comprising at least one field effect transistor having a low threshold voltage and a saturation resistor, and logical circuit made by that process

Info

Publication number
DE3264586D1
DE3264586D1 DE8282402181T DE3264586T DE3264586D1 DE 3264586 D1 DE3264586 D1 DE 3264586D1 DE 8282402181 T DE8282402181 T DE 8282402181T DE 3264586 T DE3264586 T DE 3264586T DE 3264586 D1 DE3264586 D1 DE 3264586D1
Authority
DE
Germany
Prior art keywords
threshold voltage
field effect
effect transistor
low threshold
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282402181T
Other languages
German (de)
English (en)
Inventor
Christian Arnodo
Gerard Nuzillat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE3264586D1 publication Critical patent/DE3264586D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N89/00—Integrated devices, or assemblies of multiple devices, comprising at least one bulk negative resistance effect element covered by group H10N80/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE8282402181T 1981-12-09 1982-11-30 Integrated process for manufacturing logical circuits comprising at least one field effect transistor having a low threshold voltage and a saturation resistor, and logical circuit made by that process Expired DE3264586D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8123026A FR2517882A1 (fr) 1981-12-09 1981-12-09 Procede collectif de fabrication de circuits logiques comportant au moins un transistor a effet de champ du type a faible tension de seuil et une resistance saturable, et circuit logique realise par un tel procede

Publications (1)

Publication Number Publication Date
DE3264586D1 true DE3264586D1 (en) 1985-08-08

Family

ID=9264838

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282402181T Expired DE3264586D1 (en) 1981-12-09 1982-11-30 Integrated process for manufacturing logical circuits comprising at least one field effect transistor having a low threshold voltage and a saturation resistor, and logical circuit made by that process

Country Status (4)

Country Link
EP (1) EP0081422B1 (enExample)
JP (1) JPS58107651A (enExample)
DE (1) DE3264586D1 (enExample)
FR (1) FR2517882A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0628336B2 (ja) * 1984-10-29 1994-04-13 富士通株式会社 論理回路
JPS6288355A (ja) * 1985-10-15 1987-04-22 Nec Corp Ｉｃ用抵抗体

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2449369A1 (fr) * 1979-02-13 1980-09-12 Thomson Csf Circuit logique comportant une resistance saturable

Also Published As

Publication number Publication date
JPS58107651A (ja) 1983-06-27
EP0081422A2 (fr) 1983-06-15
FR2517882A1 (fr) 1983-06-10
EP0081422A3 (en) 1983-07-20
FR2517882B1 (enExample) 1984-01-27
EP0081422B1 (fr) 1985-07-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee