DE3174815D1 - Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor - Google Patents

Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor

Info

Publication number
DE3174815D1
DE3174815D1 DE8181108563T DE3174815T DE3174815D1 DE 3174815 D1 DE3174815 D1 DE 3174815D1 DE 8181108563 T DE8181108563 T DE 8181108563T DE 3174815 T DE3174815 T DE 3174815T DE 3174815 D1 DE3174815 D1 DE 3174815D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
integrated semiconductor
capacitor
forming
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181108563T
Other languages
English (en)
Inventor
Joseph Francis Shepard
Paul Jamin Tsang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3174815D1 publication Critical patent/DE3174815D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/98—Utilizing process equivalents or options

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8181108563T 1980-12-17 1981-10-20 Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor Expired DE3174815D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/217,371 US4403394A (en) 1980-12-17 1980-12-17 Formation of bit lines for ram device

Publications (1)

Publication Number Publication Date
DE3174815D1 true DE3174815D1 (en) 1986-07-17

Family

ID=22810796

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181108563T Expired DE3174815D1 (en) 1980-12-17 1981-10-20 Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor

Country Status (4)

Country Link
US (1) US4403394A (de)
EP (1) EP0054129B1 (de)
JP (1) JPS57107071A (de)
DE (1) DE3174815D1 (de)

Families Citing this family (26)

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US4536941A (en) * 1980-03-21 1985-08-27 Kuo Chang Kiang Method of making high density dynamic memory cell
JPS5940571A (ja) * 1982-08-30 1984-03-06 Hitachi Ltd 半導体装置
US4569122A (en) * 1983-03-09 1986-02-11 Advanced Micro Devices, Inc. Method of forming a low resistance quasi-buried contact
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
JPS6014462A (ja) * 1983-07-05 1985-01-25 Oki Electric Ind Co Ltd 半導体メモリ素子
JPS6018948A (ja) * 1983-07-12 1985-01-31 Nec Corp 半導体集積回路装置
NL8303179A (nl) * 1983-09-15 1985-04-01 Philips Nv Halfgeleiderinrichting.
JPS60132353A (ja) * 1983-12-20 1985-07-15 Mitsubishi Electric Corp 半導体装置の製造方法
JPS60163455A (ja) * 1984-02-03 1985-08-26 Toshiba Corp 読み出し専用記憶装置及びその製造方法
JPH0640572B2 (ja) * 1984-05-21 1994-05-25 沖電気工業株式会社 半導体装置の製造方法
JPH0673369B2 (ja) * 1984-06-15 1994-09-14 沖電気工業株式会社 半導体装置
EP0222795B1 (de) * 1985-05-03 1990-09-26 AT&T Corp. Polycidverfahren bei der halbleiterherstellung
JPS62136069A (ja) * 1985-12-10 1987-06-19 Hitachi Ltd 半導体装置およびその製造方法
US4755480A (en) * 1986-02-03 1988-07-05 Intel Corporation Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition
US4786612A (en) * 1986-02-03 1988-11-22 Intel Corporation Plasma enhanced chemical vapor deposited vertical silicon nitride resistor
JPS62260340A (ja) * 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
US4808555A (en) * 1986-07-10 1989-02-28 Motorola, Inc. Multiple step formation of conductive material layers
JPS63128750A (ja) * 1986-11-19 1988-06-01 Toshiba Corp 半導体装置
JP2681887B2 (ja) * 1987-03-06 1997-11-26 シ−メンス、アクチエンゲゼルシヤフト ３次元１トランジスタメモリセル構造とその製法
US4992391A (en) * 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET
US5006481A (en) * 1989-11-30 1991-04-09 Sgs-Thomson Microelectronics, Inc. Method of making a stacked capacitor DRAM cell
US5116776A (en) * 1989-11-30 1992-05-26 Sgs-Thomson Microelectronics, Inc. Method of making a stacked copacitor for dram cell
US5037772A (en) * 1989-12-13 1991-08-06 Texas Instruments Incorporated Method for forming a polysilicon to polysilicon capacitor
KR100247724B1 (ko) * 1995-09-01 2000-03-15 포만 제프리 엘 실리사이드화된 접촉 영역을 갖는 확산 저항 구조 및 그의 제조 방법
US20060110913A1 (en) * 2004-11-24 2006-05-25 Haiwei Xin Gate structure having diffusion barrier layer

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element
US4240092A (en) * 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
US4102714A (en) * 1976-04-23 1978-07-25 International Business Machines Corporation Process for fabricating a low breakdown voltage device for polysilicon gate technology
DE2737073C3 (de) * 1977-08-17 1981-09-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen eines Isolierschicht-Feldeffekttransistors für eine Ein-Transistor-Speicherzelle
DE2815605C3 (de) * 1978-04-11 1981-04-16 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher mit Ansteuerleitungen hoher Leitfähigkeit
US4251571A (en) * 1978-05-02 1981-02-17 International Business Machines Corporation Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
US4264382A (en) * 1978-05-25 1981-04-28 International Business Machines Corporation Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions
US4200968A (en) * 1978-08-09 1980-05-06 Harris Corporation VMOS transistor and method of fabrication
DE2837877C2 (de) * 1978-08-30 1987-04-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers
JPS5856268B2 (ja) * 1978-12-26 1983-12-14 超エル・エス・アイ技術研究組合 半導体装置の製造方法
JPS6055988B2 (ja) * 1979-01-26 1985-12-07 株式会社日立製作所 半導体装置の製法
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
JPS5621372A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor device
JPS5826829B2 (ja) * 1979-08-30 1983-06-06 富士通株式会社 ダイナミックメモリセルの製造方法
US4272302A (en) * 1979-09-05 1981-06-09 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method of making V-MOS field effect transistors utilizing a two-step anisotropic etching and ion implantation
US4369564A (en) * 1979-10-29 1983-01-25 American Microsystems, Inc. VMOS Memory cell and method for making same
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
US4326332A (en) * 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
IE52791B1 (en) * 1980-11-05 1988-03-02 Fujitsu Ltd Semiconductor devices
US4341009A (en) * 1980-12-05 1982-07-27 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
US4356211A (en) * 1980-12-19 1982-10-26 International Business Machines Corporation Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon

Also Published As

Publication number Publication date
EP0054129B1 (de) 1986-06-11
JPS57107071A (en) 1982-07-03
EP0054129A2 (de) 1982-06-23
JPH0152907B2 (de) 1989-11-10
EP0054129A3 (en) 1983-08-24
US4403394A (en) 1983-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee