DE3168092D1 - A method of manufacturing a semiconductor device, and a device so manufactured - Google Patents

A method of manufacturing a semiconductor device, and a device so manufactured

Info

Publication number
DE3168092D1
DE3168092D1 DE8181300648T DE3168092T DE3168092D1 DE 3168092 D1 DE3168092 D1 DE 3168092D1 DE 8181300648 T DE8181300648 T DE 8181300648T DE 3168092 T DE3168092 T DE 3168092T DE 3168092 D1 DE3168092 D1 DE 3168092D1
Authority
DE
Germany
Prior art keywords
manufactured
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181300648T
Other languages
English (en)
Inventor
Kazumasa Nawata
Hirokazu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
VLSI Technology Research Association
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VLSI Technology Research Association filed Critical VLSI Technology Research Association
Application granted granted Critical
Publication of DE3168092D1 publication Critical patent/DE3168092D1/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/923Diffusion through a layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
DE8181300648T 1980-02-18 1981-02-18 A method of manufacturing a semiconductor device, and a device so manufactured Expired DE3168092D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1879180A JPS56115525A (en) 1980-02-18 1980-02-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
DE3168092D1 true DE3168092D1 (en) 1985-02-21

Family

ID=11981421

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181300648T Expired DE3168092D1 (en) 1980-02-18 1981-02-18 A method of manufacturing a semiconductor device, and a device so manufactured

Country Status (4)

Country Link
US (1) US4375999A (de)
EP (1) EP0034910B1 (de)
JP (1) JPS56115525A (de)
DE (1) DE3168092D1 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476157A (en) * 1981-07-29 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing schottky barrier diode
JPS5933860A (ja) * 1982-08-19 1984-02-23 Toshiba Corp 半導体装置およびその製造方法
JPS6057952A (ja) * 1983-09-09 1985-04-03 Toshiba Corp 半導体装置の製造方法
JPS60117765A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd 半導体装置の製造方法
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell
US4764480A (en) * 1985-04-01 1988-08-16 National Semiconductor Corporation Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size
US5100824A (en) * 1985-04-01 1992-03-31 National Semiconductor Corporation Method of making small contactless RAM cell
US4766094A (en) * 1986-03-21 1988-08-23 Hollinger Theodore G Semiconductor doping process
US4764482A (en) * 1986-11-21 1988-08-16 General Electric Company Method of fabricating an integrated circuit containing bipolar and MOS transistors
KR890005885A (ko) * 1987-09-26 1989-05-17 강진구 바이폴라 트랜지스터의 제조방법
GB8810973D0 (en) * 1988-05-10 1988-06-15 Stc Plc Improvements in integrated circuits
US5318917A (en) * 1988-11-04 1994-06-07 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
US5204274A (en) * 1988-11-04 1993-04-20 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
US5204276A (en) * 1988-12-06 1993-04-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH0817180B2 (ja) * 1989-06-27 1996-02-21 株式会社東芝 半導体装置の製造方法
US5304831A (en) * 1990-12-21 1994-04-19 Siliconix Incorporated Low on-resistance power MOS technology
US5404040A (en) * 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
JPH0766925B2 (ja) * 1990-12-26 1995-07-19 財団法人韓国電子通信研究所 ガリウム砒素金属半導体電界効果トランジスタの製造方法
US5128272A (en) * 1991-06-18 1992-07-07 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process
JPH05102175A (ja) * 1991-10-07 1993-04-23 Sharp Corp 半導体装置の製造方法
US5358883A (en) * 1992-02-03 1994-10-25 Motorola, Inc. Lateral bipolar transistor
GB2266606B (en) * 1992-04-27 1996-02-14 Intel Corp A microprocessor with an external command mode
DE4300806C1 (de) * 1993-01-14 1993-12-23 Siemens Ag Verfahren zur Herstellung von vertikalen MOS-Transistoren
KR0138352B1 (ko) * 1993-12-17 1998-04-28 김광호 반도체 장치 및 그의 제조방법
JP3409618B2 (ja) * 1996-12-26 2003-05-26 ソニー株式会社 半導体装置の製造方法
US6127211A (en) * 1997-10-02 2000-10-03 Matsushita Electric Industrial Co., Ltd. Method of manufacturing transistor
US7067383B2 (en) * 2004-03-08 2006-06-27 Intersil Americas, Inc. Method of making bipolar transistors and resulting product
US7556999B2 (en) * 2006-09-12 2009-07-07 Macronix International Co., Ltd. Method for fabricating non-volatile memory
US9484451B2 (en) * 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617929A (en) * 1968-12-30 1971-11-02 Texas Instruments Inc Junction laser devices having a mode-suppressing region and methods of fabrication
JPS49131384A (de) * 1973-04-18 1974-12-17
DE2429957B2 (de) * 1974-06-21 1980-08-28 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines bestimmten Leitungstyps in einem Halbleiterkörper
US4074304A (en) * 1974-10-04 1978-02-14 Nippon Electric Company, Ltd. Semiconductor device having a miniature junction area and process for fabricating same
JPS51127682A (en) * 1975-04-30 1976-11-06 Fujitsu Ltd Manufacturing process of semiconductor device
US4063973A (en) * 1975-11-10 1977-12-20 Tokyo Shibaura Electric Co., Ltd. Method of making a semiconductor device
US4085499A (en) * 1975-12-29 1978-04-25 Matsushita Electric Industrial Co., Ltd. Method of making a MOS-type semiconductor device
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS5317081A (en) * 1976-07-30 1978-02-16 Sharp Corp Production of i2l device
DE2640465A1 (de) * 1976-09-08 1978-03-09 Siemens Ag Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat
DE2715158A1 (de) * 1977-04-05 1978-10-19 Licentia Gmbh Verfahren zur herstellung mindestens einer mit mindestens einer i hoch 2 l-schaltung integrierten analogschaltung
DE2739662A1 (de) * 1977-09-02 1979-03-08 Siemens Ag Verfahren zur herstellung von mos-transistoren
JPS5461489A (en) * 1977-10-26 1979-05-17 Toshiba Corp Manufacture for semiconductor device
JPS555861A (en) * 1978-06-29 1980-01-17 Sumitomo Electric Ind Ltd Method of manufacturing porous tube
US4305760A (en) * 1978-12-22 1981-12-15 Ncr Corporation Polysilicon-to-substrate contact processing

Also Published As

Publication number Publication date
EP0034910B1 (de) 1985-01-09
US4375999A (en) 1983-03-08
EP0034910A1 (de) 1981-09-02
JPS56115525A (en) 1981-09-10

Similar Documents

Publication Publication Date Title
DE3168092D1 (en) A method of manufacturing a semiconductor device, and a device so manufactured
US4352724B1 (en) Method of manufacturing a semiconductor device
GB2081159B (en) Method of manufacturing a semiconductor device
DE3168239D1 (en) A method of manufacturing a semiconductor device, and a device, for example a bomis fet, so manufactured
DE3167203D1 (en) Method of manufacturing a semiconductor device
DE3271995D1 (en) Method of manufacturing a semiconductor device
DE3174468D1 (en) Semiconductor device and method of manufacturing the same
EP0030457A3 (en) Method of manufacturing a semiconductor device and a semiconductor device manufactured by the method
JPS56152272A (en) Method of manufacturing semiconductor device
JPS56140671A (en) Method of manufacturing semiconductor device
DE3168688D1 (en) Method for manufacturing a semiconductor device
DE3473384D1 (en) Semiconductor device and a method of manufacturing the same
DE3164132D1 (en) Method of manufacturing a semiconductor device and semiconductor device manufactured by using said method
JPS56144545A (en) Method of manufacturing semiconductor device
DE3463317D1 (en) Method of manufacturing a semiconductor device and semiconductor device manufactured by means of the method
DE3175085D1 (en) Method of manufacturing a semiconductor device
JPS56144543A (en) Method of manufacturing semiconductor device
JPS56140668A (en) Method of manufacturing semiconductor device
JPS56114352A (en) Method of manufacturing semiconductor device
DE3175081D1 (en) Method of manufacturing a semiconductor device of the mis type
DE3164835D1 (en) Method of manufacturing a semiconductor device containing a schottky barrier, and device
JPS571260A (en) Semiconductor device and method of manufacturing same
DE3070994D1 (en) A semiconductor device and a method of manufacturing a semiconductor device
DE3063768D1 (en) A method of manufacturing a semiconductor device
GB2081160B (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU LTD., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee