DE3071489D1 - Method of manufacturing a semiconductor device with a schottky junction - Google Patents

Method of manufacturing a semiconductor device with a schottky junction

Info

Publication number
DE3071489D1
DE3071489D1 DE8080107315T DE3071489T DE3071489D1 DE 3071489 D1 DE3071489 D1 DE 3071489D1 DE 8080107315 T DE8080107315 T DE 8080107315T DE 3071489 T DE3071489 T DE 3071489T DE 3071489 D1 DE3071489 D1 DE 3071489D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
schottky junction
schottky
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080107315T
Other languages
English (en)
Inventor
Kazuyoshi Shinada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
VLSI Technology Research Association
Original Assignee
VLSI Technology Research Association
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP15460079A external-priority patent/JPS5678153A/ja
Priority claimed from JP15460179A external-priority patent/JPS5678154A/ja
Application filed by VLSI Technology Research Association filed Critical VLSI Technology Research Association
Application granted granted Critical
Publication of DE3071489D1 publication Critical patent/DE3071489D1/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8226Bipolar technology comprising merged transistor logic or integrated injection logic
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/092Laser beam processing-diodes or transistor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/093Laser beam treatment in general

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8080107315T 1979-11-29 1980-11-24 Method of manufacturing a semiconductor device with a schottky junction Expired DE3071489D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP15460079A JPS5678153A (en) 1979-11-29 1979-11-29 Manufacture of semiconductor device
JP15460179A JPS5678154A (en) 1979-11-29 1979-11-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
DE3071489D1 true DE3071489D1 (en) 1986-04-17

Family

ID=26482843

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080107315T Expired DE3071489D1 (en) 1979-11-29 1980-11-24 Method of manufacturing a semiconductor device with a schottky junction

Country Status (3)

Country Link
US (1) US4338139A (de)
EP (1) EP0029986B1 (de)
DE (1) DE3071489D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936432B2 (ja) * 1980-08-25 1984-09-04 株式会社東芝 半導体装置の製造方法
JPS5861622A (ja) * 1981-10-09 1983-04-12 Hitachi Ltd 単結晶薄膜の製造方法
JPS59125640A (ja) * 1982-12-28 1984-07-20 Fujitsu Ltd 半導体装置の製造方法
US4619036A (en) * 1984-09-28 1986-10-28 Texas Instruments Incorporated Self-aligned low-temperature emitter drive-in
US4610730A (en) * 1984-12-20 1986-09-09 Trw Inc. Fabrication process for bipolar devices
EP0258962A3 (de) * 1986-09-05 1988-08-03 THORN EMI North America Inc. Halbleiteranordnungen mit selektiven Verbindungen und ein Verfahren zu deren Herstellung
US4818712A (en) * 1987-10-13 1989-04-04 Northrop Corporation Aluminum liftoff masking process and product
US5189297A (en) * 1988-08-29 1993-02-23 Santa Barbara Research Center Planar double-layer heterojunction HgCdTe photodiodes and methods for fabricating same
US5495121A (en) * 1991-09-30 1996-02-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JPH07235602A (ja) * 1994-02-21 1995-09-05 Mitsubishi Electric Corp Iil回路を有する半導体装置およびその製造方法
FR2937279A1 (fr) * 2008-10-22 2010-04-23 Arjowiggins Document de securite comportant des elements thermochromiques et une information renseignant sur une temperature

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4199775A (en) * 1974-09-03 1980-04-22 Bell Telephone Laboratories, Incorporated Integrated circuit and method for fabrication thereof
US4160989A (en) * 1975-12-29 1979-07-10 U.S. Philips Corporation Integrated circuit having complementary bipolar transistors
DE2705444A1 (de) * 1977-02-09 1978-08-10 Siemens Ag Verfahren zur lokal begrenzten erwaermung eines festkoerpers
US4156246A (en) * 1977-05-25 1979-05-22 Bell Telephone Laboratories, Incorporated Combined ohmic and Schottky output transistors for logic circuit
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
US4243433A (en) * 1978-01-18 1981-01-06 Gibbons James F Forming controlled inset regions by ion implantation and laser bombardment
US4181538A (en) * 1978-09-26 1980-01-01 The United States Of America As Represented By The United States Department Of Energy Method for making defect-free zone by laser-annealing of doped silicon
US4214918A (en) * 1978-10-12 1980-07-29 Stanford University Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam
US4229232A (en) * 1978-12-11 1980-10-21 Spire Corporation Method involving pulsed beam processing of metallic and dielectric materials
US4254428A (en) * 1979-12-28 1981-03-03 International Business Machines Corporation Self-aligned Schottky diode structure and method of fabrication
US4269631A (en) * 1980-01-14 1981-05-26 International Business Machines Corporation Selective epitaxy method using laser annealing for making filamentary transistors

Also Published As

Publication number Publication date
EP0029986B1 (de) 1986-03-12
EP0029986A2 (de) 1981-06-10
US4338139A (en) 1982-07-06
EP0029986A3 (en) 1983-10-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee