DE3030653C2 - Verfahren zur Herstellung von Halbleiteranordnungen - Google Patents

Verfahren zur Herstellung von Halbleiteranordnungen

Info

Publication number
DE3030653C2
DE3030653C2 DE3030653A DE3030653A DE3030653C2 DE 3030653 C2 DE3030653 C2 DE 3030653C2 DE 3030653 A DE3030653 A DE 3030653A DE 3030653 A DE3030653 A DE 3030653A DE 3030653 C2 DE3030653 C2 DE 3030653C2
Authority
DE
Germany
Prior art keywords
film
resist film
resist
contact hole
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3030653A
Other languages
German (de)
English (en)
Other versions
DE3030653A1 (de
Inventor
Kozo Tachikawa Tokyo Mochiji
Fumio Hachioji Tokyo Murai
Shinji Urawa Saitama Okazaki
Susumu Tokyo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3030653A1 publication Critical patent/DE3030653A1/de
Application granted granted Critical
Publication of DE3030653C2 publication Critical patent/DE3030653C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE3030653A 1979-08-13 1980-08-13 Verfahren zur Herstellung von Halbleiteranordnungen Expired DE3030653C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10224579A JPS5626450A (en) 1979-08-13 1979-08-13 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
DE3030653A1 DE3030653A1 (de) 1981-02-26
DE3030653C2 true DE3030653C2 (de) 1984-02-23

Family

ID=14322219

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3030653A Expired DE3030653C2 (de) 1979-08-13 1980-08-13 Verfahren zur Herstellung von Halbleiteranordnungen

Country Status (4)

Country Link
US (1) US4315984A (en, 2012)
JP (1) JPS5626450A (en, 2012)
DE (1) DE3030653C2 (en, 2012)
NL (1) NL184755C (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3446789A1 (de) * 1984-12-21 1986-07-03 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Verfahren zum herstellen von halbleiterbauelementen

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3216823A1 (de) * 1982-05-05 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von strukturen von aus metallsilizid und polysilizium bestehenden doppelschichten auf integrierte halbleiterschaltungen enthaltenden substraten durch reaktives ionenaetzen
US4579812A (en) * 1984-02-03 1986-04-01 Advanced Micro Devices, Inc. Process for forming slots of different types in self-aligned relationship using a latent image mask
JPS61117832A (ja) * 1984-11-14 1986-06-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2570709B2 (ja) * 1986-10-28 1997-01-16 ソニー株式会社 エツチング方法
JPH0750704B2 (ja) * 1987-03-20 1995-05-31 富士通株式会社 半導体装置の製造方法
US5049972A (en) * 1988-01-29 1991-09-17 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US4855252A (en) * 1988-08-22 1989-08-08 International Business Machines Corporation Process for making self-aligned contacts
US4997746A (en) * 1988-11-22 1991-03-05 Greco Nancy A Method of forming conductive lines and studs
JP2794118B2 (ja) * 1989-05-16 1998-09-03 三菱電機株式会社 微細パターンの形成方法
US4985374A (en) * 1989-06-30 1991-01-15 Kabushiki Kaisha Toshiba Making a semiconductor device with ammonia treatment of photoresist
JPH03278432A (ja) * 1990-03-28 1991-12-10 Kawasaki Steel Corp 半導体装置の配線形成方法
US5290664A (en) * 1990-03-29 1994-03-01 Sharp Kabushiki Kaisha Method for preparing electrode for semiconductor device
US5407785A (en) * 1992-12-18 1995-04-18 Vlsi Technology, Inc. Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures
US5478779A (en) 1994-03-07 1995-12-26 Micron Technology, Inc. Electrically conductive projections and semiconductor processing method of forming same
US5326428A (en) * 1993-09-03 1994-07-05 Micron Semiconductor, Inc. Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
US6025116A (en) * 1997-03-31 2000-02-15 Siemens Aktiengesellschaft Etching of contact holes
US6146986A (en) * 1999-01-08 2000-11-14 Lam Research Corporation Lithographic method for creating damascene metallization layers
US6174801B1 (en) 1999-03-05 2001-01-16 Taiwan Semiconductor Manufacturing Company E-beam direct writing to pattern step profiles of dielectric layers applied to fill poly via with poly line, contact with metal line, and metal via with metal line
JP2001015479A (ja) * 1999-06-29 2001-01-19 Toshiba Corp 半導体装置の製造方法
US6528934B1 (en) 2000-05-30 2003-03-04 Chunghwa Picture Tubes Ltd. Beam forming region for electron gun
US6524937B1 (en) * 2000-08-23 2003-02-25 Tyco Electronics Corp. Selective T-gate process
RU2282227C2 (ru) * 2004-10-20 2006-08-20 ООО Деловой центр "Кронштадт" Способ формирования элементов из каталитических металлов на поверхности сенсора
JP2008047932A (ja) * 2007-09-18 2008-02-28 Nec Lcd Technologies Ltd 薄膜トランジスタの製造方法
JP2008022028A (ja) * 2007-09-18 2008-01-31 Nec Lcd Technologies Ltd 薄膜トランジスタの製造方法
FR2921751B1 (fr) * 2007-10-02 2009-12-18 St Microelectronics Crolles 2 Procede de realisation de dispositif semi-conducteur a architecture asymetrique
US8455312B2 (en) * 2011-09-12 2013-06-04 Cindy X. Qiu Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3649393A (en) * 1970-06-12 1972-03-14 Ibm Variable depth etching of film layers using variable exposures of photoresists
US3930857A (en) * 1973-05-03 1976-01-06 International Business Machines Corporation Resist process
US4035522A (en) * 1974-07-19 1977-07-12 International Business Machines Corporation X-ray lithography mask
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
US4001061A (en) * 1975-03-05 1977-01-04 International Business Machines Corporation Single lithography for multiple-layer bubble domain devices
US4040891A (en) * 1976-06-30 1977-08-09 Ibm Corporation Etching process utilizing the same positive photoresist layer for two etching steps

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3446789A1 (de) * 1984-12-21 1986-07-03 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Verfahren zum herstellen von halbleiterbauelementen

Also Published As

Publication number Publication date
US4315984A (en) 1982-02-16
NL184755B (nl) 1989-05-16
DE3030653A1 (de) 1981-02-26
JPS6323657B2 (en, 2012) 1988-05-17
NL8004586A (nl) 1981-02-17
NL184755C (nl) 1989-10-16
JPS5626450A (en) 1981-03-14

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING. SCHUEBE

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee