DE2843791A1 - Monolithisch integrierte verknuepfungsschaltung aus feldeffekttransistoren - Google Patents
Monolithisch integrierte verknuepfungsschaltung aus feldeffekttransistorenInfo
- Publication number
- DE2843791A1 DE2843791A1 DE19782843791 DE2843791A DE2843791A1 DE 2843791 A1 DE2843791 A1 DE 2843791A1 DE 19782843791 DE19782843791 DE 19782843791 DE 2843791 A DE2843791 A DE 2843791A DE 2843791 A1 DE2843791 A1 DE 2843791A1
- Authority
- DE
- Germany
- Prior art keywords
- logic circuit
- operating potential
- field effect
- signal
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 claims description 37
- 230000000694 effects Effects 0.000 claims description 4
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 claims 1
- 230000006399 behavior Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009916 joint effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Static Random-Access Memory (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19782843791 DE2843791A1 (de) | 1978-10-06 | 1978-10-06 | Monolithisch integrierte verknuepfungsschaltung aus feldeffekttransistoren |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19782843791 DE2843791A1 (de) | 1978-10-06 | 1978-10-06 | Monolithisch integrierte verknuepfungsschaltung aus feldeffekttransistoren |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2843791A1 true DE2843791A1 (de) | 1980-04-17 |
| DE2843791C2 DE2843791C2 (cs) | 1987-11-05 |
Family
ID=6051643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19782843791 Granted DE2843791A1 (de) | 1978-10-06 | 1978-10-06 | Monolithisch integrierte verknuepfungsschaltung aus feldeffekttransistoren |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE2843791A1 (cs) |
-
1978
- 1978-10-06 DE DE19782843791 patent/DE2843791A1/de active Granted
Non-Patent Citations (2)
| Title |
|---|
| DE-Buch BECKER/MÄDER: Hochintegrierte MOS-Schal- tungen, 1972, S.95 u.96 * |
| IEEE Journal of Solid-State Circuits, Vol.SC-8, No.6, Dez. 1973, S.462-469 * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2843791C2 (cs) | 1987-11-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8363 | Opposition against the patent | ||
| 8365 | Fully valid after opposition proceedings | ||
| 8339 | Ceased/non-payment of the annual fee |