DE2837877A1 - Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung - Google Patents

Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung

Info

Publication number
DE2837877A1
DE2837877A1 DE19782837877 DE2837877A DE2837877A1 DE 2837877 A1 DE2837877 A1 DE 2837877A1 DE 19782837877 DE19782837877 DE 19782837877 DE 2837877 A DE2837877 A DE 2837877A DE 2837877 A1 DE2837877 A1 DE 2837877A1
Authority
DE
Germany
Prior art keywords
memory cells
layer
bit lines
insulation layer
mos transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19782837877
Other languages
German (de)
English (en)
Other versions
DE2837877C2 (US06373033-20020416-M00035.png
Inventor
Kurt Dr Hoffmann
Heinrich Dipl Phys Schulte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19782837877 priority Critical patent/DE2837877A1/de
Priority to US06/067,926 priority patent/US4334236A/en
Priority to GB7929716A priority patent/GB2029103B/en
Priority to JP11015479A priority patent/JPS5534500A/ja
Priority to FR7921664A priority patent/FR2435106A1/fr
Publication of DE2837877A1 publication Critical patent/DE2837877A1/de
Application granted granted Critical
Publication of DE2837877C2 publication Critical patent/DE2837877C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
DE19782837877 1978-08-30 1978-08-30 Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung Granted DE2837877A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE19782837877 DE2837877A1 (de) 1978-08-30 1978-08-30 Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung
US06/067,926 US4334236A (en) 1978-08-30 1979-08-20 One-transistor dynamic ram with poly bit lines
GB7929716A GB2029103B (en) 1978-08-30 1979-08-28 Mos-integrated semiconductor store
JP11015479A JPS5534500A (en) 1978-08-30 1979-08-29 Integrated mos semiconductor memory and method of manufacturing same
FR7921664A FR2435106A1 (fr) 1978-08-30 1979-08-29 Memoire a semi-conducteurs integree selon la technique mos et procede pour sa fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782837877 DE2837877A1 (de) 1978-08-30 1978-08-30 Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung

Publications (2)

Publication Number Publication Date
DE2837877A1 true DE2837877A1 (de) 1980-03-06
DE2837877C2 DE2837877C2 (US06373033-20020416-M00035.png) 1987-04-23

Family

ID=6048279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782837877 Granted DE2837877A1 (de) 1978-08-30 1978-08-30 Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung

Country Status (5)

Country Link
US (1) US4334236A (US06373033-20020416-M00035.png)
JP (1) JPS5534500A (US06373033-20020416-M00035.png)
DE (1) DE2837877A1 (US06373033-20020416-M00035.png)
FR (1) FR2435106A1 (US06373033-20020416-M00035.png)
GB (1) GB2029103B (US06373033-20020416-M00035.png)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240195A (en) * 1978-09-15 1980-12-23 Bell Telephone Laboratories, Incorporated Dynamic random access memory
EP0154685B1 (en) * 1980-01-25 1990-04-18 Kabushiki Kaisha Toshiba Semiconductor memory device
US4536941A (en) * 1980-03-21 1985-08-27 Kuo Chang Kiang Method of making high density dynamic memory cell
US4883543A (en) * 1980-06-05 1989-11-28 Texas Instruments Incroporated Shielding for implant in manufacture of dynamic memory
JPS5718356A (en) * 1980-07-07 1982-01-30 Mitsubishi Electric Corp Semiconductor memory storage
JPS5793572A (en) * 1980-12-03 1982-06-10 Nec Corp Manufacture of semiconductor device
DE3046218C2 (de) * 1980-12-08 1982-09-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Erzeugung einer Eintransistor-Speicherzelle in Doppelsilizium-Technik
US4403394A (en) * 1980-12-17 1983-09-13 International Business Machines Corporation Formation of bit lines for ram device
JPS5831568A (ja) * 1981-08-18 1983-02-24 Nec Corp 半導体メモリ
US4453176A (en) * 1981-12-31 1984-06-05 International Business Machines Corporation LSI Chip carrier with buried repairable capacitor with low inductance leads
US4887135A (en) * 1982-02-09 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Dual level polysilicon single transistor-capacitor memory array
US4574465A (en) * 1982-04-13 1986-03-11 Texas Instruments Incorporated Differing field oxide thicknesses in dynamic memory device
US4652898A (en) * 1984-07-19 1987-03-24 International Business Machines Corporation High speed merged charge memory
US4774203A (en) * 1985-10-25 1988-09-27 Hitachi, Ltd. Method for making static random-access memory device
JPH0831565B2 (ja) * 1986-08-05 1996-03-27 三菱電機株式会社 ランダムアクセスメモリ
US5087951A (en) * 1988-05-02 1992-02-11 Micron Technology Semiconductor memory device transistor and cell structure
US10707296B2 (en) * 2018-10-10 2020-07-07 Texas Instruments Incorporated LOCOS with sidewall spacer for different capacitance density capacitors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2431079A1 (de) * 1974-06-28 1976-02-12 Ibm Deutschland Dynamischer halbleiterspeicher mit zwei-tranistor-speicherelementen
DE2619849A1 (de) * 1975-05-05 1976-11-18 Intel Corp Speicherbauteil in integrierter schaltungstechnik
DE2705757A1 (de) * 1976-02-13 1977-08-18 Tokyo Shibaura Electric Co Ram-speicher
JPS5390888A (en) 1977-01-21 1978-08-10 Nec Corp Integrated circuit device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4164751A (en) * 1976-11-10 1979-08-14 Texas Instruments Incorporated High capacity dynamic ram cell
US4112575A (en) * 1976-12-20 1978-09-12 Texas Instruments Incorporated Fabrication methods for the high capacity ram cell
US4240195A (en) * 1978-09-15 1980-12-23 Bell Telephone Laboratories, Incorporated Dynamic random access memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2431079A1 (de) * 1974-06-28 1976-02-12 Ibm Deutschland Dynamischer halbleiterspeicher mit zwei-tranistor-speicherelementen
DE2619849A1 (de) * 1975-05-05 1976-11-18 Intel Corp Speicherbauteil in integrierter schaltungstechnik
DE2705757A1 (de) * 1976-02-13 1977-08-18 Tokyo Shibaura Electric Co Ram-speicher
JPS5390888A (en) 1977-01-21 1978-08-10 Nec Corp Integrated circuit device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
1976 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, S. 128, 129 *
JP-OS 90888/78 *

Also Published As

Publication number Publication date
US4334236A (en) 1982-06-08
DE2837877C2 (US06373033-20020416-M00035.png) 1987-04-23
GB2029103B (en) 1983-03-09
GB2029103A (en) 1980-03-12
FR2435106B1 (US06373033-20020416-M00035.png) 1984-05-04
FR2435106A1 (fr) 1980-03-28
JPS5534500A (en) 1980-03-11

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
D2 Grant after examination
8364 No opposition during term of opposition