DE2837852C2 - Prozessor zum gleichzeitigen Ermitteln und Bereitstellen zweier Adressen von Befehls- und/oder Datenwortregistern eines bereichsweise adressierbaren Hauptspeichers - Google Patents

Prozessor zum gleichzeitigen Ermitteln und Bereitstellen zweier Adressen von Befehls- und/oder Datenwortregistern eines bereichsweise adressierbaren Hauptspeichers

Info

Publication number
DE2837852C2
DE2837852C2 DE2837852A DE2837852A DE2837852C2 DE 2837852 C2 DE2837852 C2 DE 2837852C2 DE 2837852 A DE2837852 A DE 2837852A DE 2837852 A DE2837852 A DE 2837852A DE 2837852 C2 DE2837852 C2 DE 2837852C2
Authority
DE
Germany
Prior art keywords
control
register
word
memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2837852A
Other languages
German (de)
English (en)
Other versions
DE2837852A1 (de
Inventor
Barry Raymond Gynedd Valley Pa. Borgerson
Merlin LeRoy Arden Hills Minn. Hanson
Garold Stephen Doylestown Pa. Tjaden
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Sperry Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Corp filed Critical Sperry Corp
Publication of DE2837852A1 publication Critical patent/DE2837852A1/de
Application granted granted Critical
Publication of DE2837852C2 publication Critical patent/DE2837852C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
DE2837852A 1977-09-02 1978-08-30 Prozessor zum gleichzeitigen Ermitteln und Bereitstellen zweier Adressen von Befehls- und/oder Datenwortregistern eines bereichsweise adressierbaren Hauptspeichers Expired DE2837852C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/830,303 US4199811A (en) 1977-09-02 1977-09-02 Microprogrammable computer utilizing concurrently operating processors

Publications (2)

Publication Number Publication Date
DE2837852A1 DE2837852A1 (de) 1979-03-08
DE2837852C2 true DE2837852C2 (de) 1985-10-03

Family

ID=25256708

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2837852A Expired DE2837852C2 (de) 1977-09-02 1978-08-30 Prozessor zum gleichzeitigen Ermitteln und Bereitstellen zweier Adressen von Befehls- und/oder Datenwortregistern eines bereichsweise adressierbaren Hauptspeichers

Country Status (7)

Country Link
US (1) US4199811A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5496335A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1114955A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2837852C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2402251B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2005056B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT1099022B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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US4550382A (en) * 1982-09-21 1985-10-29 Xerox Corporation Filtered inputs
JPS59132070A (ja) * 1983-01-18 1984-07-30 Mitsubishi Electric Corp アレイ演算用デ−タ処理装置
US4720784A (en) * 1983-10-18 1988-01-19 Thiruvengadam Radhakrishnan Multicomputer network
CA1223969A (en) * 1984-10-31 1987-07-07 William M. Johnson Microcode control of a parallel architecture microprocessor
JPH0766329B2 (ja) * 1985-06-14 1995-07-19 株式会社日立製作所 情報処理装置
US4748585A (en) * 1985-12-26 1988-05-31 Chiarulli Donald M Processor utilizing reconfigurable process segments to accomodate data word length
US4833599A (en) * 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
JPH02190930A (ja) * 1988-12-29 1990-07-26 Internatl Business Mach Corp <Ibm> ソフトウエア命令実行装置
DE69029995T2 (de) * 1989-11-09 1997-08-21 Ibm Multiprozessor mit relativ atomaren Befehlen
US5210839A (en) * 1990-12-21 1993-05-11 Sun Microsystems, Inc. Method and apparatus for providing a memory address from a computer instruction using a mask register
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5586277A (en) * 1994-03-01 1996-12-17 Intel Corporation Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5673427A (en) * 1994-03-01 1997-09-30 Intel Corporation Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
US5537629A (en) * 1994-03-01 1996-07-16 Intel Corporation Decoder for single cycle decoding of single prefixes in variable length instructions
US5600806A (en) * 1994-03-01 1997-02-04 Intel Corporation Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US5566298A (en) * 1994-03-01 1996-10-15 Intel Corporation Method for state recovery during assist and restart in a decoder having an alias mechanism
US5559974A (en) * 1994-03-01 1996-09-24 Intel Corporation Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation
US5758116A (en) * 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5867701A (en) * 1995-06-12 1999-02-02 Intel Corporation System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow
US5815724A (en) * 1996-03-29 1998-09-29 Intel Corporation Method and apparatus for controlling power consumption in a microprocessor
US6996813B1 (en) 2000-10-31 2006-02-07 Sun Microsystems, Inc. Frameworks for loading and execution of object-based programs
US7096466B2 (en) 2001-03-26 2006-08-22 Sun Microsystems, Inc. Loading attribute for partial loading of class files into virtual machines
US7020874B2 (en) * 2001-03-26 2006-03-28 Sun Microsystems, Inc. Techniques for loading class files into virtual machines
US7543288B2 (en) * 2001-03-27 2009-06-02 Sun Microsystems, Inc. Reduced instruction set for Java virtual machines
US6957428B2 (en) 2001-03-27 2005-10-18 Sun Microsystems, Inc. Enhanced virtual machine instructions
US7039904B2 (en) * 2001-08-24 2006-05-02 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions for storing values into local variables
US7058934B2 (en) 2001-08-24 2006-06-06 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions for instantiating Java objects
US6988261B2 (en) * 2001-08-24 2006-01-17 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions in Java computing environments
US7228533B2 (en) * 2001-08-24 2007-06-05 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions for performing programming loops
US6938241B1 (en) * 2001-12-10 2005-08-30 Lsi Logic Corporation Compiler independent bit-field macros
US7698539B1 (en) * 2003-07-16 2010-04-13 Banning John P System and method of instruction modification

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US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
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Also Published As

Publication number Publication date
JPS6311697B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-03-15
FR2402251B1 (fr) 1986-09-05
IT7827237A0 (it) 1978-08-31
CA1114955A (en) 1981-12-22
FR2402251A1 (fr) 1979-03-30
JPS5496335A (en) 1979-07-30
GB2005056A (en) 1979-04-11
GB2005056B (en) 1982-02-03
DE2837852A1 (de) 1979-03-08
IT1099022B (it) 1985-09-18
US4199811A (en) 1980-04-22

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
OI Miscellaneous see part 1
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee