DE69132129T2 - In der Grundzahl 4 arbeitende Übertragvorgriffsbäume - Google Patents

In der Grundzahl 4 arbeitende Übertragvorgriffsbäume

Info

Publication number
DE69132129T2
DE69132129T2 DE69132129T DE69132129T DE69132129T2 DE 69132129 T2 DE69132129 T2 DE 69132129T2 DE 69132129 T DE69132129 T DE 69132129T DE 69132129 T DE69132129 T DE 69132129T DE 69132129 T2 DE69132129 T2 DE 69132129T2
Authority
DE
Germany
Prior art keywords
trees
ahead
look
working
basic number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132129T
Other languages
English (en)
Other versions
DE69132129D1 (de
Inventor
Thomas W Lynch
Steven D Mcintyre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69132129D1 publication Critical patent/DE69132129D1/de
Application granted granted Critical
Publication of DE69132129T2 publication Critical patent/DE69132129T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
DE69132129T 1990-04-02 1991-02-20 In der Grundzahl 4 arbeitende Übertragvorgriffsbäume Expired - Fee Related DE69132129T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/503,822 US5095458A (en) 1990-04-02 1990-04-02 Radix 4 carry lookahead tree and redundant cell therefor

Publications (2)

Publication Number Publication Date
DE69132129D1 DE69132129D1 (de) 2000-05-31
DE69132129T2 true DE69132129T2 (de) 2000-12-21

Family

ID=24003660

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132129T Expired - Fee Related DE69132129T2 (de) 1990-04-02 1991-02-20 In der Grundzahl 4 arbeitende Übertragvorgriffsbäume

Country Status (5)

Country Link
US (1) US5095458A (de)
EP (1) EP0450755B1 (de)
JP (1) JPH0773019A (de)
AT (1) ATE192245T1 (de)
DE (1) DE69132129T2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479356A (en) * 1990-10-18 1995-12-26 Hewlett-Packard Company Computer-aided method of designing a carry-lookahead adder
US5355473A (en) * 1991-06-20 1994-10-11 Lawrence Au Indexed record locating and counting mechanism
KR940007926B1 (ko) * 1992-05-20 1994-08-29 삼성전자 주식회사 가산기
US5270955A (en) * 1992-07-31 1993-12-14 Texas Instruments Incorporated Method of detecting arithmetic or logical computation result
EP0590251A2 (de) * 1992-09-22 1994-04-06 Motorola, Inc. Hochgeschwindigkeitsaddierer
EP0651321B1 (de) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5574928A (en) * 1993-10-29 1996-11-12 Advanced Micro Devices, Inc. Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
US5495579A (en) * 1994-03-25 1996-02-27 Bull Hn Information Systems Inc. Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count
US5689693A (en) * 1994-04-26 1997-11-18 Advanced Micro Devices, Inc. Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus
US5619441A (en) * 1994-10-14 1997-04-08 International Business Machines Corporation High speed dynamic binary incrementer
US5668984A (en) * 1995-02-27 1997-09-16 International Business Machines Corporation Variable stage load path and method of operation
US5646875A (en) * 1995-02-27 1997-07-08 International Business Machines Corporation Denormalization system and method of operation
US5748516A (en) * 1995-09-26 1998-05-05 Advanced Micro Devices, Inc. Floating point processing unit with forced arithmetic results
US5878266A (en) * 1995-09-26 1999-03-02 Advanced Micro Devices, Inc. Reservation station for a floating point processing unit
US5761105A (en) * 1995-09-26 1998-06-02 Advanced Micro Devices, Inc. Reservation station including addressable constant store for a floating point processing unit
US5754812A (en) * 1995-10-06 1998-05-19 Advanced Micro Devices, Inc. Out-of-order load/store execution control
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
US6038657A (en) * 1995-10-06 2000-03-14 Advanced Micro Devices, Inc. Scan chains for out-of-order load/store execution control
US5944777A (en) * 1997-05-05 1999-08-31 Intel Corporation Method and apparatus for generating carries in an adder circuit
US8396824B2 (en) * 1998-05-28 2013-03-12 Qps Tech. Limited Liability Company Automatic data categorization with optimally spaced semantic seed terms
US20070294229A1 (en) * 1998-05-28 2007-12-20 Q-Phrase Llc Chat conversation methods traversing a provisional scaffold of meanings
US7711672B2 (en) * 1998-05-28 2010-05-04 Lawrence Au Semantic network methods to disambiguate natural language meaning
US6438572B1 (en) 1998-09-21 2002-08-20 Rn2R, L.L.C. Adder having reduced number of internal layers and method of operation thereof
US6496846B1 (en) * 1999-07-13 2002-12-17 Hewlett-Packard Company Conditional carry encoding for carry select adder
US6523049B1 (en) 1999-12-21 2003-02-18 International Business Machines Corporation Circuit and method for determining greater than or equal to three out of sixty-six
US6259275B1 (en) 2000-05-01 2001-07-10 Rn2R, L.L.C. Logic gate having reduced power dissipation and method of operation thereof
US7007059B1 (en) * 2001-07-30 2006-02-28 Cypress Semiconductor Corporation Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization
US7062499B2 (en) * 2002-01-08 2006-06-13 Intel Corporation Enhanced multiway radix tree and related methods
US6591286B1 (en) 2002-01-18 2003-07-08 Neomagic Corp. Pipelined carry-lookahead generation for a fast incrementer
KR100714316B1 (ko) * 2004-10-22 2007-05-02 광주과학기술원 혼합형 가산기
EP2080120A2 (de) * 2006-10-03 2009-07-22 Qps Tech. Limited Liability Company Mechanismus zur automatischen abstimmung von host-mit-gast-inhalt über kategorisierung
US7904499B2 (en) * 2007-04-16 2011-03-08 Sony Computer Entertainment Inc. Methods and apparatus for carry generation in a binary look ahead system
US10171105B2 (en) * 2016-08-25 2019-01-01 International Business Machines Corporation Carry-less population count

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163211A (en) * 1978-04-17 1979-07-31 Fujitsu Limited Tree-type combinatorial logic circuit
US4660165A (en) * 1984-04-03 1987-04-21 Trw Inc. Pyramid carry adder circuit
EP0239749B1 (de) * 1986-03-05 1990-07-25 Holger Sedlak Kryptographie-Verfahren und Kryptographie-Prozessor zur Durchführung des Verfahrens
JPH01250137A (ja) * 1987-12-17 1989-10-05 Mitsubishi Electric Corp 加算回路
US4858168A (en) * 1988-02-16 1989-08-15 American Telephone And Telegraph Company Carry look-ahead technique having a reduced number of logic levels
US4899305A (en) * 1988-06-15 1990-02-06 National Semiconductor Corp. Manchester carry adder circuit
US4956802A (en) * 1988-12-14 1990-09-11 Sun Microsystems, Inc. Method and apparatus for a parallel carry generation adder
US4905180A (en) * 1988-12-16 1990-02-27 Intel Corporation MOS adder with minimum pass gates in carry line

Also Published As

Publication number Publication date
EP0450755A3 (en) 1993-01-27
JPH0773019A (ja) 1995-03-17
ATE192245T1 (de) 2000-05-15
EP0450755A2 (de) 1991-10-09
DE69132129D1 (de) 2000-05-31
EP0450755B1 (de) 2000-04-26
US5095458A (en) 1992-03-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee