IT1099022B - Calcolatore microprogrammabile utilizzante unita' di elaborazione operanti simultaneamente - Google Patents

Calcolatore microprogrammabile utilizzante unita' di elaborazione operanti simultaneamente

Info

Publication number
IT1099022B
IT1099022B IT27237/78A IT2723778A IT1099022B IT 1099022 B IT1099022 B IT 1099022B IT 27237/78 A IT27237/78 A IT 27237/78A IT 2723778 A IT2723778 A IT 2723778A IT 1099022 B IT1099022 B IT 1099022B
Authority
IT
Italy
Prior art keywords
microprogrammable
calculator
processing unit
unit operating
operating simultaneously
Prior art date
Application number
IT27237/78A
Other languages
English (en)
Other versions
IT7827237A0 (it
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of IT7827237A0 publication Critical patent/IT7827237A0/it
Application granted granted Critical
Publication of IT1099022B publication Critical patent/IT1099022B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
IT27237/78A 1977-09-02 1978-08-31 Calcolatore microprogrammabile utilizzante unita' di elaborazione operanti simultaneamente IT1099022B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/830,303 US4199811A (en) 1977-09-02 1977-09-02 Microprogrammable computer utilizing concurrently operating processors

Publications (2)

Publication Number Publication Date
IT7827237A0 IT7827237A0 (it) 1978-08-31
IT1099022B true IT1099022B (it) 1985-09-18

Family

ID=25256708

Family Applications (1)

Application Number Title Priority Date Filing Date
IT27237/78A IT1099022B (it) 1977-09-02 1978-08-31 Calcolatore microprogrammabile utilizzante unita' di elaborazione operanti simultaneamente

Country Status (7)

Country Link
US (1) US4199811A (it)
JP (1) JPS5496335A (it)
CA (1) CA1114955A (it)
DE (1) DE2837852C2 (it)
FR (1) FR2402251B1 (it)
GB (1) GB2005056B (it)
IT (1) IT1099022B (it)

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US4550382A (en) * 1982-09-21 1985-10-29 Xerox Corporation Filtered inputs
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US4870644A (en) * 1982-09-21 1989-09-26 Xerox Corporation Control crash diagnostic strategy and RAM display
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US4720784A (en) * 1983-10-18 1988-01-19 Thiruvengadam Radhakrishnan Multicomputer network
CA1223969A (en) * 1984-10-31 1987-07-07 William M. Johnson Microcode control of a parallel architecture microprocessor
JPH0766329B2 (ja) * 1985-06-14 1995-07-19 株式会社日立製作所 情報処理装置
US4748585A (en) * 1985-12-26 1988-05-31 Chiarulli Donald M Processor utilizing reconfigurable process segments to accomodate data word length
US4833599A (en) * 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
US5179703A (en) * 1987-11-17 1993-01-12 International Business Machines Corporation Dynamically adaptive environment for computer programs
JPH02190930A (ja) * 1988-12-29 1990-07-26 Internatl Business Mach Corp <Ibm> ソフトウエア命令実行装置
EP0432075B1 (en) * 1989-11-09 1997-02-26 International Business Machines Corporation Multiprocessor with relatively atomic instructions
US5210839A (en) * 1990-12-21 1993-05-11 Sun Microsystems, Inc. Method and apparatus for providing a memory address from a computer instruction using a mask register
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5673427A (en) * 1994-03-01 1997-09-30 Intel Corporation Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
US5537629A (en) * 1994-03-01 1996-07-16 Intel Corporation Decoder for single cycle decoding of single prefixes in variable length instructions
US5566298A (en) * 1994-03-01 1996-10-15 Intel Corporation Method for state recovery during assist and restart in a decoder having an alias mechanism
US5600806A (en) * 1994-03-01 1997-02-04 Intel Corporation Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US5559974A (en) * 1994-03-01 1996-09-24 Intel Corporation Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5586277A (en) * 1994-03-01 1996-12-17 Intel Corporation Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
US5758116A (en) * 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5867701A (en) * 1995-06-12 1999-02-02 Intel Corporation System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow
US5815724A (en) * 1996-03-29 1998-09-29 Intel Corporation Method and apparatus for controlling power consumption in a microprocessor
US6996813B1 (en) 2000-10-31 2006-02-07 Sun Microsystems, Inc. Frameworks for loading and execution of object-based programs
US7020874B2 (en) * 2001-03-26 2006-03-28 Sun Microsystems, Inc. Techniques for loading class files into virtual machines
US7096466B2 (en) 2001-03-26 2006-08-22 Sun Microsystems, Inc. Loading attribute for partial loading of class files into virtual machines
US7543288B2 (en) 2001-03-27 2009-06-02 Sun Microsystems, Inc. Reduced instruction set for Java virtual machines
US6957428B2 (en) 2001-03-27 2005-10-18 Sun Microsystems, Inc. Enhanced virtual machine instructions
US7039904B2 (en) * 2001-08-24 2006-05-02 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions for storing values into local variables
US7228533B2 (en) * 2001-08-24 2007-06-05 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions for performing programming loops
US7058934B2 (en) 2001-08-24 2006-06-06 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions for instantiating Java objects
US6988261B2 (en) * 2001-08-24 2006-01-17 Sun Microsystems, Inc. Frameworks for generation of Java macro instructions in Java computing environments
US6938241B1 (en) * 2001-12-10 2005-08-30 Lsi Logic Corporation Compiler independent bit-field macros
US7698539B1 (en) * 2003-07-16 2010-04-13 Banning John P System and method of instruction modification

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US3380025A (en) * 1964-12-04 1968-04-23 Ibm Microprogrammed addressing control system for a digital computer
US3421150A (en) * 1966-08-26 1969-01-07 Sperry Rand Corp Multiprocessor interrupt directory
US3470540A (en) * 1967-04-24 1969-09-30 Rca Corp Multiprocessing computer system with special instruction sequencing
US3593300A (en) * 1967-11-13 1971-07-13 Ibm Arrangement for automatically selecting units for task executions in data processing systems
US3641505A (en) * 1969-06-25 1972-02-08 Bell Telephone Labor Inc Multiprocessor computer adapted for partitioning into a plurality of independently operating systems
US3631405A (en) * 1969-11-12 1971-12-28 Honeywell Inc Sharing of microprograms between processors
FR2136845B1 (it) * 1971-05-07 1973-05-11 Inf Cie Intern
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FR2253435A5 (it) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
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US4071890A (en) * 1976-11-29 1978-01-31 Data General Corporation CPU-Synchronous parallel data processor apparatus
US4077060A (en) * 1976-12-27 1978-02-28 International Business Machines Corporation Asymmetrical multiprocessor system

Also Published As

Publication number Publication date
GB2005056A (en) 1979-04-11
CA1114955A (en) 1981-12-22
GB2005056B (en) 1982-02-03
JPS5496335A (en) 1979-07-30
DE2837852A1 (de) 1979-03-08
FR2402251B1 (fr) 1986-09-05
DE2837852C2 (de) 1985-10-03
JPS6311697B2 (it) 1988-03-15
IT7827237A0 (it) 1978-08-31
US4199811A (en) 1980-04-22
FR2402251A1 (fr) 1979-03-30

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