DE2659660A1 - Eingangspufferschaltung fuer speicherschaltungen - Google Patents
Eingangspufferschaltung fuer speicherschaltungenInfo
- Publication number
- DE2659660A1 DE2659660A1 DE19762659660 DE2659660A DE2659660A1 DE 2659660 A1 DE2659660 A1 DE 2659660A1 DE 19762659660 DE19762659660 DE 19762659660 DE 2659660 A DE2659660 A DE 2659660A DE 2659660 A1 DE2659660 A1 DE 2659660A1
- Authority
- DE
- Germany
- Prior art keywords
- node
- potential
- buffer circuit
- nodes
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000872 buffer Substances 0.000 title claims description 39
- 230000015654 memory Effects 0.000 title claims description 27
- 230000005669 field effect Effects 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 12
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 230000008929 regeneration Effects 0.000 claims description 8
- 238000011069 regeneration method Methods 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 7
- 101150018711 AASS gene Proteins 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
- H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356086—Bistable circuits with additional means for controlling the main nodes
- H03K3/356095—Bistable circuits with additional means for controlling the main nodes with synchronous operation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/669,012 US4038567A (en) | 1976-03-22 | 1976-03-22 | Memory input signal buffer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2659660A1 true DE2659660A1 (de) | 1977-09-29 |
Family
ID=24684663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19762659660 Withdrawn DE2659660A1 (de) | 1976-03-22 | 1976-12-30 | Eingangspufferschaltung fuer speicherschaltungen |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4038567A (enExample) |
| JP (1) | JPS52115131A (enExample) |
| DE (1) | DE2659660A1 (enExample) |
| FR (1) | FR2345858A1 (enExample) |
| GB (1) | GB1567492A (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4110639A (en) * | 1976-12-09 | 1978-08-29 | Texas Instruments Incorporated | Address buffer circuit for high speed semiconductor memory |
| US4130892A (en) * | 1977-01-03 | 1978-12-19 | Rockwell International Corporation | Radiation hard memory cell and array thereof |
| US4146802A (en) * | 1977-09-19 | 1979-03-27 | Motorola, Inc. | Self latching buffer |
| DE2838817A1 (de) * | 1978-09-06 | 1980-03-20 | Ibm Deutschland | Ttl-kompatible adressverriegelungsschaltung mit feldeffekttransistoren und entsprechendes betriebsverfahren |
| US4250412A (en) * | 1979-03-05 | 1981-02-10 | Motorola, Inc. | Dynamic output buffer |
| USRE31663E (en) * | 1979-03-05 | 1984-09-04 | Motorola, Inc. | Dynamic output buffer |
| USRE31662E (en) * | 1979-03-05 | 1984-09-04 | Motorola, Inc. | Output buffer with voltage sustainer circuit |
| WO1980001965A1 (en) * | 1979-03-13 | 1980-09-18 | Ncr Co | Static volatile/non-volatile ram system |
| JPS5951073B2 (ja) * | 1980-03-27 | 1984-12-12 | 富士通株式会社 | 半導体記憶装置 |
| JPS57147194A (en) * | 1981-03-05 | 1982-09-10 | Fujitsu Ltd | Address buffer |
| US4496857A (en) * | 1982-11-01 | 1985-01-29 | International Business Machines Corporation | High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels |
| DE4009785A1 (de) * | 1990-03-27 | 1991-10-02 | Licentia Gmbh | Integrierte flip-flop-schaltung |
| US5097144A (en) * | 1990-04-30 | 1992-03-17 | International Business Machines Corporation | Driver circuit for testing bi-directional transceiver semiconductor products |
| US5477173A (en) * | 1993-07-30 | 1995-12-19 | Santa Barbara Research Center | Ultra low power gain circuit (UGC) |
| US5491428A (en) * | 1993-12-20 | 1996-02-13 | Hitachi Microsystems, Inc. | Bus-isolating pre-charge buffer |
| EP0996226B1 (en) * | 1998-10-23 | 2006-05-03 | Nippon Telegraph and Telephone Corporation | Voltage comparator |
| JP4617840B2 (ja) * | 2004-11-17 | 2011-01-26 | 日本電気株式会社 | ブートストラップ回路及びその駆動方法並びにシフトレジスタ回路、論理演算回路、半導体装置 |
| US8553463B1 (en) * | 2011-03-21 | 2013-10-08 | Lattice Semiconductor Corporation | Voltage discharge circuit having divided discharge current |
| KR102171262B1 (ko) | 2013-12-26 | 2020-10-28 | 삼성전자 주식회사 | 입력 버퍼와 입력 버퍼를 포함하는 플래쉬 메모리 장치 |
| WO2015187482A1 (en) * | 2014-06-03 | 2015-12-10 | Yale University | Bootstrapping circuit and unipolar logic circuits using the same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE756139A (fr) * | 1969-09-15 | 1971-02-15 | Rca Corp | Circuit intermediaire integre pour le couplage d'un circuit de commandea impedance de sortie faible a une charge a impedance d'entree elevee |
| US3760381A (en) * | 1972-06-30 | 1973-09-18 | Ibm | Stored charge memory detection circuit |
| US3835457A (en) * | 1972-12-07 | 1974-09-10 | Motorola Inc | Dynamic mos ttl compatible |
| DE2309192C3 (de) * | 1973-02-23 | 1975-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Regenerierschaltung nach Art eines getasteten Flipflops und Verfahren zum Betrieb einer solchen Regenerierschaltung |
| US3891977A (en) * | 1974-07-15 | 1975-06-24 | Fairchild Camera Instr Co | Charge coupled memory device |
| US3949381A (en) * | 1974-07-23 | 1976-04-06 | International Business Machines Corporation | Differential charge transfer sense amplifier |
| US3959781A (en) * | 1974-11-04 | 1976-05-25 | Intel Corporation | Semiconductor random access memory |
-
1976
- 1976-03-22 US US05/669,012 patent/US4038567A/en not_active Expired - Lifetime
- 1976-12-30 DE DE19762659660 patent/DE2659660A1/de not_active Withdrawn
-
1977
- 1977-02-01 FR FR7703511A patent/FR2345858A1/fr active Granted
- 1977-02-15 GB GB6325/77A patent/GB1567492A/en not_active Expired
- 1977-02-18 JP JP1630877A patent/JPS52115131A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB1567492A (en) | 1980-05-14 |
| US4038567A (en) | 1977-07-26 |
| JPS52115131A (en) | 1977-09-27 |
| FR2345858B1 (enExample) | 1979-03-09 |
| FR2345858A1 (fr) | 1977-10-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8139 | Disposal/non-payment of the annual fee |