FR2345858A1 - Circuit tampon pour signaux d'entree de memoires - Google Patents

Circuit tampon pour signaux d'entree de memoires

Info

Publication number
FR2345858A1
FR2345858A1 FR7703511A FR7703511A FR2345858A1 FR 2345858 A1 FR2345858 A1 FR 2345858A1 FR 7703511 A FR7703511 A FR 7703511A FR 7703511 A FR7703511 A FR 7703511A FR 2345858 A1 FR2345858 A1 FR 2345858A1
Authority
FR
France
Prior art keywords
input signals
buffer circuit
memory input
memory
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7703511A
Other languages
English (en)
Other versions
FR2345858B1 (fr
Inventor
Scott C Lewis
Theodore M Redman
James E Rock
Donald L Wilder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2345858A1 publication Critical patent/FR2345858A1/fr
Application granted granted Critical
Publication of FR2345858B1 publication Critical patent/FR2345858B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356086—Bistable circuits with additional means for controlling the main nodes
    • H03K3/356095—Bistable circuits with additional means for controlling the main nodes with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
FR7703511A 1976-03-22 1977-02-01 Circuit tampon pour signaux d'entree de memoires Granted FR2345858A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/669,012 US4038567A (en) 1976-03-22 1976-03-22 Memory input signal buffer circuit

Publications (2)

Publication Number Publication Date
FR2345858A1 true FR2345858A1 (fr) 1977-10-21
FR2345858B1 FR2345858B1 (fr) 1979-03-09

Family

ID=24684663

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7703511A Granted FR2345858A1 (fr) 1976-03-22 1977-02-01 Circuit tampon pour signaux d'entree de memoires

Country Status (5)

Country Link
US (1) US4038567A (fr)
JP (1) JPS52115131A (fr)
DE (1) DE2659660A1 (fr)
FR (1) FR2345858A1 (fr)
GB (1) GB1567492A (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110639A (en) * 1976-12-09 1978-08-29 Texas Instruments Incorporated Address buffer circuit for high speed semiconductor memory
US4130892A (en) * 1977-01-03 1978-12-19 Rockwell International Corporation Radiation hard memory cell and array thereof
US4146802A (en) * 1977-09-19 1979-03-27 Motorola, Inc. Self latching buffer
DE2838817A1 (de) * 1978-09-06 1980-03-20 Ibm Deutschland Ttl-kompatible adressverriegelungsschaltung mit feldeffekttransistoren und entsprechendes betriebsverfahren
US4250412A (en) * 1979-03-05 1981-02-10 Motorola, Inc. Dynamic output buffer
USRE31662E (en) * 1979-03-05 1984-09-04 Motorola, Inc. Output buffer with voltage sustainer circuit
USRE31663E (en) * 1979-03-05 1984-09-04 Motorola, Inc. Dynamic output buffer
JPS56500109A (fr) * 1979-03-13 1981-02-05
JPS5951073B2 (ja) * 1980-03-27 1984-12-12 富士通株式会社 半導体記憶装置
JPS57147194A (en) * 1981-03-05 1982-09-10 Fujitsu Ltd Address buffer
US4496857A (en) * 1982-11-01 1985-01-29 International Business Machines Corporation High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels
DE4009785A1 (de) * 1990-03-27 1991-10-02 Licentia Gmbh Integrierte flip-flop-schaltung
US5097144A (en) * 1990-04-30 1992-03-17 International Business Machines Corporation Driver circuit for testing bi-directional transceiver semiconductor products
US5477173A (en) * 1993-07-30 1995-12-19 Santa Barbara Research Center Ultra low power gain circuit (UGC)
US5491428A (en) * 1993-12-20 1996-02-13 Hitachi Microsystems, Inc. Bus-isolating pre-charge buffer
EP0996226B1 (fr) * 1998-10-23 2006-05-03 Nippon Telegraph and Telephone Corporation Comparateur de tension
JP4617840B2 (ja) * 2004-11-17 2011-01-26 日本電気株式会社 ブートストラップ回路及びその駆動方法並びにシフトレジスタ回路、論理演算回路、半導体装置
US8553463B1 (en) * 2011-03-21 2013-10-08 Lattice Semiconductor Corporation Voltage discharge circuit having divided discharge current
KR102171262B1 (ko) 2013-12-26 2020-10-28 삼성전자 주식회사 입력 버퍼와 입력 버퍼를 포함하는 플래쉬 메모리 장치
CN106664081A (zh) * 2014-06-03 2017-05-10 耶鲁大学 自举电路及使用自举电路的单极性逻辑电路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756139A (fr) * 1969-09-15 1971-02-15 Rca Corp Circuit intermediaire integre pour le couplage d'un circuit de commandea impedance de sortie faible a une charge a impedance d'entree elevee
US3760381A (en) * 1972-06-30 1973-09-18 Ibm Stored charge memory detection circuit
US3835457A (en) * 1972-12-07 1974-09-10 Motorola Inc Dynamic mos ttl compatible
DE2309192C3 (de) * 1973-02-23 1975-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Regenerierschaltung nach Art eines getasteten Flipflops und Verfahren zum Betrieb einer solchen Regenerierschaltung
US3891977A (en) * 1974-07-15 1975-06-24 Fairchild Camera Instr Co Charge coupled memory device
US3949381A (en) * 1974-07-23 1976-04-06 International Business Machines Corporation Differential charge transfer sense amplifier
US3959781A (en) * 1974-11-04 1976-05-25 Intel Corporation Semiconductor random access memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, VOLUME 13, NO. 11, AVRIL 1971, IBM CORP.NEW-YORK USA HAUG ET AUTRES: "FET STORAGE CELL", PAGE 3478) *
IBM TECHNICAL DISCLOSURE BULLETIN, VOLUME 15, NO. 9, FEVRIER 1973, IBM CORP., NEW-YORK USA BAINTINGER ET AUTRES: "EIGHT-DEVICE STORAGE CELL", PAGES 2861 - 2862 *

Also Published As

Publication number Publication date
DE2659660A1 (de) 1977-09-29
FR2345858B1 (fr) 1979-03-09
JPS52115131A (en) 1977-09-27
GB1567492A (en) 1980-05-14
US4038567A (en) 1977-07-26

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Legal Events

Date Code Title Description
ST Notification of lapse