DE2635800C2 - Monolithisch integrierte Schottky-I↑2↑L-Gatterschaltung - Google Patents

Monolithisch integrierte Schottky-I↑2↑L-Gatterschaltung

Info

Publication number
DE2635800C2
DE2635800C2 DE2635800A DE2635800A DE2635800C2 DE 2635800 C2 DE2635800 C2 DE 2635800C2 DE 2635800 A DE2635800 A DE 2635800A DE 2635800 A DE2635800 A DE 2635800A DE 2635800 C2 DE2635800 C2 DE 2635800C2
Authority
DE
Germany
Prior art keywords
zone
gate circuit
base
transistor
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2635800A
Other languages
German (de)
English (en)
Other versions
DE2635800A1 (de
Inventor
Masanori Yokohama Nakai
Yukuya Tokumaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP50096787A external-priority patent/JPS5220755A/ja
Priority claimed from JP50096786A external-priority patent/JPS5220754A/ja
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE2635800A1 publication Critical patent/DE2635800A1/de
Application granted granted Critical
Publication of DE2635800C2 publication Critical patent/DE2635800C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H10D84/652—Integrated injection logic using vertical injector structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/091—Integrated injection logic or merged transistor logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Bipolar Integrated Circuits (AREA)
DE2635800A 1975-08-09 1976-08-09 Monolithisch integrierte Schottky-I↑2↑L-Gatterschaltung Expired DE2635800C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP50096787A JPS5220755A (en) 1975-08-09 1975-08-09 Gate circuit
JP50096786A JPS5220754A (en) 1975-08-09 1975-08-09 Gate circuit

Publications (2)

Publication Number Publication Date
DE2635800A1 DE2635800A1 (de) 1977-02-10
DE2635800C2 true DE2635800C2 (de) 1986-04-03

Family

ID=26437958

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2635800A Expired DE2635800C2 (de) 1975-08-09 1976-08-09 Monolithisch integrierte Schottky-I↑2↑L-Gatterschaltung

Country Status (4)

Country Link
US (1) US4110634A (OSRAM)
DE (1) DE2635800C2 (OSRAM)
FR (1) FR2321216A1 (OSRAM)
GB (1) GB1542314A (OSRAM)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4243895A (en) * 1978-01-04 1981-01-06 Nazarian Artashes R Integrated injection circuit
US5023482A (en) * 1982-03-29 1991-06-11 North American Philips Corp. ISL to TTL translator
US4542331A (en) * 1983-08-01 1985-09-17 Signetics Corporation Low-impedance voltage reference
CN101470409B (zh) * 2007-12-26 2010-11-10 鸿富锦精密工业（深圳）有限公司 激光装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL261720A (OSRAM) * 1960-03-04
DE2262297C2 (de) * 1972-12-20 1985-11-28 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierbare, logisch verknüpfbare Halbleiterschaltungsanordnung mit I↑2↑L-Aufbau
GB1434961A (en) * 1973-11-08 1976-05-12 Plessey Co Ltd Integrated circuit arrangements
US3986045A (en) * 1975-04-23 1976-10-12 Advanced Micro Devices, Inc. High speed logic level converter
US3987310A (en) * 1975-06-19 1976-10-19 Motorola, Inc. Schottky diode - complementary transistor logic

Also Published As

Publication number Publication date
US4110634A (en) 1978-08-29
GB1542314A (en) 1979-03-14
FR2321216A1 (fr) 1977-03-11
DE2635800A1 (de) 1977-02-10
FR2321216B1 (OSRAM) 1983-01-14

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: HENKEL, G., DR.PHIL. FEILER, L., DR.RER.NAT. HAENZ

D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP