DE2632050A1 - Verfahren zum herstellen eines isolierschichtbereichs in der oberflaeche eines halbleiterkoerpers - Google Patents

Verfahren zum herstellen eines isolierschichtbereichs in der oberflaeche eines halbleiterkoerpers

Info

Publication number
DE2632050A1
DE2632050A1 DE19762632050 DE2632050A DE2632050A1 DE 2632050 A1 DE2632050 A1 DE 2632050A1 DE 19762632050 DE19762632050 DE 19762632050 DE 2632050 A DE2632050 A DE 2632050A DE 2632050 A1 DE2632050 A1 DE 2632050A1
Authority
DE
Germany
Prior art keywords
layer
insulating
anodic oxidation
semiconductor material
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762632050
Other languages
German (de)
English (en)
Inventor
Jun Charles R Cook
U Aung San
Raymond E Scherrer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of DE2632050A1 publication Critical patent/DE2632050A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
DE19762632050 1975-08-04 1976-07-16 Verfahren zum herstellen eines isolierschichtbereichs in der oberflaeche eines halbleiterkoerpers Withdrawn DE2632050A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US60185575A 1975-08-04 1975-08-04

Publications (1)

Publication Number Publication Date
DE2632050A1 true DE2632050A1 (de) 1977-02-24

Family

ID=24409032

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762632050 Withdrawn DE2632050A1 (de) 1975-08-04 1976-07-16 Verfahren zum herstellen eines isolierschichtbereichs in der oberflaeche eines halbleiterkoerpers

Country Status (4)

Country Link
DE (1) DE2632050A1 (me)
FR (1) FR2320365A1 (me)
GB (1) GB1508719A (me)
IT (1) IT1075021B (me)

Also Published As

Publication number Publication date
FR2320365A1 (fr) 1977-03-04
IT1075021B (it) 1985-04-22
GB1508719A (en) 1978-04-26
FR2320365B3 (me) 1979-04-27

Similar Documents

Publication Publication Date Title
DE2640525C2 (de) Verfahren zur Herstellung einer MIS-Halbleiterschaltungsanordnung
DE2721397C3 (de) Verfahren zur Herstellung eines mindestens eine Planardiode enthaltenden HF-Halbleiterbauelementes
EP0025854B1 (de) Verfahren zum Herstellen von bipolaren Transistoren
DE2527969C2 (de) Verfahren zur Herstellung oxid- isolierter Feldeffekt-Transistoren
DE2521568A1 (de) Verfahren zum herstellen von integrierten halbleiterbauelementen
DE3014363C2 (me)
DE3037316C2 (de) Verfahren zur Herstellung von Leistungsthyristoren
DE4013643A1 (de) Bipolartransistor mit isolierter steuerelektrode und verfahren zu seiner herstellung
DE2615754C2 (me)
DE2019655C2 (de) Verfahren zur Eindiffundierung eines den Leitungstyp verändernden Aktivators in einen Oberflächenbereich eines Halbleiterkörpers
DE102018216855A1 (de) Siliziumcarbid-Halbleitervorrichtung und Verfahren zum Herstellen einer Siliziumcarbid-Halbleitervorrichtung
DE3242736A1 (de) Verfahren zum herstellen feldgesteuerter elemente mit in vertikalen kanaelen versenkten gittern, einschliesslich feldeffekt-transistoren und feldgesteuerten thyristoren
DE2641752B2 (de) Verfahren zur Herstellung eines Feldeffekttransistors
DE2550346A1 (de) Verfahren zum herstellen eines elektrisch isolierenden bereiches in dem halbleiterkoerper eines halbleiterbauelements
DE1564191B2 (de) Verfahren zum herstellen einer integrierten halbleiterschaltung mit verschiedenen, gegeneinander und gegen ein gemeinsames siliziumsubstrat elektrisch isolierten schaltungselementen
DE2718449A1 (de) Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte anordnung
DE3610890C2 (me)
DE1803024A1 (de) Integriertes Halbleiterbauelement und Verfahren zu seiner Herstellung
DE2541651C2 (de) Verfahren zur Herstellung einer Ladungsübertragungsanordnung
DE1489250A1 (de) Halbleitereinrichtung und Verfahren zu ihrer Herstellung
DE3851175T2 (de) Bipolartransistor mit Heteroübergängen.
DE2627355C3 (de) Lichtemittierende Festkörpervorrichtung und Verfahren zu deren Herstellung
DE2162219A1 (de) Verfahren zum Herstellen eines Feldeffekttransistors
DE2812728A1 (de) Doppelheterostruktur-injektionslaser und verfahren zu seiner herstellung
DE2507038C3 (de) Inverser Planartransistor und Verfahren zu seiner Herstellung

Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee