DE2620973A1 - Halbleiterschaltungsanordnung zur fet-substratvorspannungserzeugung - Google Patents

Halbleiterschaltungsanordnung zur fet-substratvorspannungserzeugung

Info

Publication number
DE2620973A1
DE2620973A1 DE19762620973 DE2620973A DE2620973A1 DE 2620973 A1 DE2620973 A1 DE 2620973A1 DE 19762620973 DE19762620973 DE 19762620973 DE 2620973 A DE2620973 A DE 2620973A DE 2620973 A1 DE2620973 A1 DE 2620973A1
Authority
DE
Germany
Prior art keywords
electrode
substrate
voltage
circuit arrangement
semiconductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19762620973
Other languages
German (de)
English (en)
Inventor
Dominic Patrick Spampinato
Lewis Madison Terman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2620973A1 publication Critical patent/DE2620973A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00Charge transfer devices
    • H10D44/40Charge-coupled devices [CCD]
    • H10D44/45Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is DC
    • G05F3/10Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205Substrate bias-voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Element Separation (AREA)
DE19762620973 1975-06-30 1976-05-12 Halbleiterschaltungsanordnung zur fet-substratvorspannungserzeugung Pending DE2620973A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US59198575A 1975-06-30 1975-06-30

Publications (1)

Publication Number Publication Date
DE2620973A1 true DE2620973A1 (de) 1977-01-27

Family

ID=24368781

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762620973 Pending DE2620973A1 (de) 1975-06-30 1976-05-12 Halbleiterschaltungsanordnung zur fet-substratvorspannungserzeugung

Country Status (4)

Country Link
JP (1) JPS525281A (enExample)
DE (1) DE2620973A1 (enExample)
FR (1) FR2316800A1 (enExample)
IT (1) IT1063327B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048474A1 (en) * 1980-09-24 1982-03-31 Kabushiki Kaisha Toshiba Self-substrate-bias circuit device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228526A (en) * 1978-12-29 1980-10-14 International Business Machines Corporation Line-addressable serial-parallel-serial array
JP3635681B2 (ja) 1994-07-15 2005-04-06 ソニー株式会社 バイアス回路の調整方法、電荷転送装置、及び電荷検出装置とその調整方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7212509A (enExample) * 1972-09-15 1974-03-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048474A1 (en) * 1980-09-24 1982-03-31 Kabushiki Kaisha Toshiba Self-substrate-bias circuit device

Also Published As

Publication number Publication date
FR2316800A1 (fr) 1977-01-28
FR2316800B1 (enExample) 1978-11-17
JPS525281A (en) 1977-01-14
IT1063327B (it) 1985-02-11

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