DE2560576C2 - Verfahren zum Herstellen einer integrierten Injektions-Schaltungsanordnung - Google Patents

Verfahren zum Herstellen einer integrierten Injektions-Schaltungsanordnung

Info

Publication number
DE2560576C2
DE2560576C2 DE2560576A DE2560576A DE2560576C2 DE 2560576 C2 DE2560576 C2 DE 2560576C2 DE 2560576 A DE2560576 A DE 2560576A DE 2560576 A DE2560576 A DE 2560576A DE 2560576 C2 DE2560576 C2 DE 2560576C2
Authority
DE
Germany
Prior art keywords
openings
semiconductor layer
layer
film
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2560576A
Other languages
German (de)
English (en)
Inventor
Shintaro Ito
Masanori Nakai
Junichi Nakamura
Yoshio Yokohama Nishi
Satoshi Shinozaki
Yukuya Tokumaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14879674A external-priority patent/JPS5426471B2/ja
Priority claimed from JP14879574A external-priority patent/JPS5513584B2/ja
Priority claimed from JP50001913A external-priority patent/JPS5182583A/ja
Priority claimed from JP14879774A external-priority patent/JPS5415396B2/ja
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Application granted granted Critical
Publication of DE2560576C2 publication Critical patent/DE2560576C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
DE2560576A 1974-12-27 1975-12-29 Verfahren zum Herstellen einer integrierten Injektions-Schaltungsanordnung Expired DE2560576C2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP14879674A JPS5426471B2 (US06534493-20030318-C00288.png) 1974-12-27 1974-12-27
JP14879574A JPS5513584B2 (US06534493-20030318-C00288.png) 1974-12-27 1974-12-27
JP50001913A JPS5182583A (en) 1974-12-27 1974-12-27 Handotaisochino seizohoho
JP14879774A JPS5415396B2 (US06534493-20030318-C00288.png) 1974-12-27 1974-12-27

Publications (1)

Publication Number Publication Date
DE2560576C2 true DE2560576C2 (de) 1985-10-31

Family

ID=27453504

Family Applications (2)

Application Number Title Priority Date Filing Date
DE2560576A Expired DE2560576C2 (de) 1974-12-27 1975-12-29 Verfahren zum Herstellen einer integrierten Injektions-Schaltungsanordnung
DE2558925A Expired DE2558925C2 (de) 1974-12-27 1975-12-29 Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE2558925A Expired DE2558925C2 (de) 1974-12-27 1975-12-29 Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung

Country Status (4)

Country Link
US (1) US4058419A (US06534493-20030318-C00288.png)
DE (2) DE2560576C2 (US06534493-20030318-C00288.png)
FR (1) FR2334204A1 (US06534493-20030318-C00288.png)
GB (1) GB1528027A (US06534493-20030318-C00288.png)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317081A (en) * 1976-07-30 1978-02-16 Sharp Corp Production of i2l device
DE2652103C2 (de) * 1976-11-16 1982-10-28 Ibm Deutschland Gmbh, 7000 Stuttgart Integrierte Halbleiteranordnung für ein logisches Schaltungskonzept und Verfahren zu ihrer Herstellung
US4180827A (en) * 1977-08-31 1979-12-25 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
CA1116309A (en) * 1977-11-30 1982-01-12 David L. Bergeron Structure and process for optimizing the characteristics of i.sup.2l devices
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques
US4317690A (en) * 1980-06-18 1982-03-02 Signetics Corporation Self-aligned double polysilicon MOS fabrication
US4446611A (en) * 1980-06-26 1984-05-08 International Business Machines Corporation Method of making a saturation-limited bipolar transistor device
DE3136731A1 (de) * 1981-09-16 1983-03-31 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung
US5759902A (en) * 1986-09-26 1998-06-02 Analog Devices, Incorporated Method of making an integrated circuit with complementary junction-isolated bipolar transistors
CN102299070A (zh) * 2010-06-22 2011-12-28 无锡华润上华半导体有限公司 横向pnp晶体管的制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328214A (en) * 1963-04-22 1967-06-27 Siliconix Inc Process for manufacturing horizontal transistor structure
US3489622A (en) * 1967-05-18 1970-01-13 Ibm Method of making high frequency transistors
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3472710A (en) * 1967-04-20 1969-10-14 Teledyne Inc Method of forming a field effect transistor
FR2051714A1 (en) * 1969-07-12 1971-04-09 Tokyo Shibaura Electric Co High frequency transistors
DE2262297C2 (de) * 1972-12-20 1985-11-28 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierbare, logisch verknüpfbare Halbleiterschaltungsanordnung mit I↑2↑L-Aufbau
US3919005A (en) * 1973-05-07 1975-11-11 Fairchild Camera Instr Co Method for fabricating double-diffused, lateral transistor
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
GB1507299A (en) * 1974-03-26 1978-04-12 Signetics Corp Integrated semiconductor devices
US3982266A (en) * 1974-12-09 1976-09-21 Texas Instruments Incorporated Integrated injection logic having high inverse current gain

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328214A (en) * 1963-04-22 1967-06-27 Siliconix Inc Process for manufacturing horizontal transistor structure
US3489622A (en) * 1967-05-18 1970-01-13 Ibm Method of making high frequency transistors
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
US-Z:"Electronics", Bd. 47, H. 20, 30. Okt. 1974, S. 111-118 *

Also Published As

Publication number Publication date
DE2558925A1 (de) 1976-07-08
DE2558925C2 (de) 1985-10-31
FR2334204B1 (US06534493-20030318-C00288.png) 1978-05-26
GB1528027A (en) 1978-10-11
FR2334204A1 (fr) 1977-07-01
US4058419A (en) 1977-11-15

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Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP