DE2556275C2 - Programmierbare logische Schaltung hoher Dichte - Google Patents

Programmierbare logische Schaltung hoher Dichte

Info

Publication number
DE2556275C2
DE2556275C2 DE2556275A DE2556275A DE2556275C2 DE 2556275 C2 DE2556275 C2 DE 2556275C2 DE 2556275 A DE2556275 A DE 2556275A DE 2556275 A DE2556275 A DE 2556275A DE 2556275 C2 DE2556275 C2 DE 2556275C2
Authority
DE
Germany
Prior art keywords
input
logic
lines
circuits
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2556275A
Other languages
German (de)
English (en)
Other versions
DE2556275A1 (de
Inventor
Dennis T. Kingston N.Y. Cox
William T. Ulster Park N.Y. Devine
Gilbert J. Red Hook N.Y. Kelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2556275A1 publication Critical patent/DE2556275A1/de
Application granted granted Critical
Publication of DE2556275C2 publication Critical patent/DE2556275C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE2556275A 1974-12-30 1975-12-13 Programmierbare logische Schaltung hoher Dichte Expired DE2556275C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/537,219 US3987287A (en) 1974-12-30 1974-12-30 High density logic array

Publications (2)

Publication Number Publication Date
DE2556275A1 DE2556275A1 (de) 1976-07-08
DE2556275C2 true DE2556275C2 (de) 1982-04-01

Family

ID=24141731

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2556275A Expired DE2556275C2 (de) 1974-12-30 1975-12-13 Programmierbare logische Schaltung hoher Dichte

Country Status (6)

Country Link
US (1) US3987287A (cg-RX-API-DMAC7.html)
JP (2) JPS5851451B2 (cg-RX-API-DMAC7.html)
CA (1) CA1047610A (cg-RX-API-DMAC7.html)
DE (1) DE2556275C2 (cg-RX-API-DMAC7.html)
GB (1) GB1473029A (cg-RX-API-DMAC7.html)
IT (1) IT1050023B (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527745A (en) 1991-03-20 1996-06-18 Crosspoint Solutions, Inc. Method of fabricating antifuses in an integrated circuit device and resulting structure

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JPS5396781A (en) * 1977-02-04 1978-08-24 Nec Corp Integrated circuit device
FR2396468A1 (fr) * 1977-06-30 1979-01-26 Ibm France Perfectionnement aux reseaux logiques programmables
US4195352A (en) * 1977-07-08 1980-03-25 Xerox Corporation Split programmable logic array
US4139907A (en) * 1977-08-31 1979-02-13 Bell Telephone Laboratories, Incorporated Integrated read only memory
US4157590A (en) * 1978-01-03 1979-06-05 International Business Machines Corporation Programmable logic array adder
JPS54148360A (en) * 1978-05-12 1979-11-20 Nec Corp Logic array circuit
JPS558135A (en) * 1978-07-04 1980-01-21 Mamoru Tanaka Rewritable programable logic array
US4348736A (en) * 1978-10-05 1982-09-07 International Business Machines Corp. Programmable logic array adder
JPS562739A (en) * 1979-06-20 1981-01-13 Nec Corp Pla logical operation circuit
US4495590A (en) * 1980-12-31 1985-01-22 International Business Machines Corporation PLA With time division multiplex feature for improved density
US4431928A (en) * 1981-06-22 1984-02-14 Hewlett-Packard Company Symmetrical programmable logic array
US4467439A (en) * 1981-06-30 1984-08-21 Ibm Corporation OR Product term function in the search array of a PLA
US4458163A (en) * 1981-07-20 1984-07-03 Texas Instruments Incorporated Programmable architecture logic
US4433331A (en) * 1981-12-14 1984-02-21 Bell Telephone Laboratories, Incorporated Programmable logic array interconnection matrix
US4461000A (en) * 1982-03-01 1984-07-17 Harris Corporation ROM/PLA Structure and method of testing
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
US4504904A (en) * 1982-06-15 1985-03-12 International Business Machines Corporation Binary logic structure employing programmable logic arrays and useful in microword generation apparatus
US4516123A (en) * 1982-12-27 1985-05-07 At&T Bell Laboratories Integrated circuit including logic array with distributed ground connections
US4791602A (en) * 1983-04-14 1988-12-13 Control Data Corporation Soft programmable logic array
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4617479B1 (en) * 1984-05-03 1993-09-21 Altera Semiconductor Corp. Programmable logic array device using eprom technology
JPS61107814A (ja) * 1984-10-31 1986-05-26 Agency Of Ind Science & Technol プログラマブル・ロジツク・アレイの構成方法
US5187393A (en) * 1986-09-19 1993-02-16 Actel Corporation Reconfigurable programmable interconnect architecture
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5172014A (en) * 1986-09-19 1992-12-15 Actel Corporation Programmable interconnect architecture
US4758745B1 (en) * 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
US5341092A (en) * 1986-09-19 1994-08-23 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US4870598A (en) * 1987-08-04 1989-09-26 Texas Instruments Incorporated Comprehensive logic circuit layout system
US5119313A (en) * 1987-08-04 1992-06-02 Texas Instruments Incorporated Comprehensive logic circuit layout system
US5150309A (en) * 1987-08-04 1992-09-22 Texas Instruments Incorporated Comprehensive logic circuit layout system
JPH02104600U (cg-RX-API-DMAC7.html) * 1989-02-06 1990-08-20
JP2544027B2 (ja) * 1990-05-24 1996-10-16 株式会社東芝 低消費電力型プログラマブルロジックアレイおよびそれを用いた情報処理装置
US5189320A (en) * 1991-09-23 1993-02-23 Atmel Corporation Programmable logic device with multiple shared logic arrays
IL103190A (en) * 1991-09-25 1995-06-29 Messier Bugatti A security locking device that includes a movable hook
WO1993012582A1 (en) * 1991-12-13 1993-06-24 Knights Technology, Inc. Programmable logic device cell and method
US5294846A (en) * 1992-08-17 1994-03-15 Paivinen John O Method and apparatus for programming anti-fuse devices
US5384497A (en) * 1992-11-04 1995-01-24 At&T Corp. Low-skew signal routing in a programmable array
US5424655A (en) * 1994-05-20 1995-06-13 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5495181A (en) * 1994-12-01 1996-02-27 Quicklogic Corporation Integrated circuit facilitating simultaneous programming of multiple antifuses
US5552720A (en) * 1994-12-01 1996-09-03 Quicklogic Corporation Method for simultaneous programming of multiple antifuses
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US20050102476A1 (en) * 2003-11-12 2005-05-12 Infineon Technologies North America Corp. Random access memory with optional column address strobe latency of one
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1101851A (en) * 1965-01-20 1968-01-31 Ncr Co Generalized logic circuitry
US3699534A (en) * 1970-12-15 1972-10-17 Us Navy Cellular arithmetic array
US3818252A (en) * 1971-12-20 1974-06-18 Hitachi Ltd Universal logical integrated circuit
US3761902A (en) * 1971-12-30 1973-09-25 Ibm Functional memory using multi-state associative cells
US3731073A (en) * 1972-04-05 1973-05-01 Bell Telephone Labor Inc Programmable switching array
US3816725A (en) * 1972-04-28 1974-06-11 Gen Electric Multiple level associative logic circuits
US3849638A (en) * 1973-07-18 1974-11-19 Gen Electric Segmented associative logic circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5527745A (en) 1991-03-20 1996-06-18 Crosspoint Solutions, Inc. Method of fabricating antifuses in an integrated circuit device and resulting structure

Also Published As

Publication number Publication date
DE2556275A1 (de) 1976-07-08
JPS6053965B2 (ja) 1985-11-28
US3987287A (en) 1976-10-19
IT1050023B (it) 1981-03-10
JPS5184538A (cg-RX-API-DMAC7.html) 1976-07-23
JPS5851451B2 (ja) 1983-11-16
GB1473029A (en) 1977-05-11
CA1047610A (en) 1979-01-30
JPS5623032A (en) 1981-03-04

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Legal Events

Date Code Title Description
OD Request for examination
8125 Change of the main classification
D2 Grant after examination
8339 Ceased/non-payment of the annual fee