DE2545513A1 - Halbleitervorrichtung und verfahren zu deren herstellung - Google Patents

Halbleitervorrichtung und verfahren zu deren herstellung

Info

Publication number
DE2545513A1
DE2545513A1 DE19752545513 DE2545513A DE2545513A1 DE 2545513 A1 DE2545513 A1 DE 2545513A1 DE 19752545513 DE19752545513 DE 19752545513 DE 2545513 A DE2545513 A DE 2545513A DE 2545513 A1 DE2545513 A1 DE 2545513A1
Authority
DE
Germany
Prior art keywords
layer
semiconductor layer
semiconductor
semiconductor substrate
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19752545513
Other languages
German (de)
English (en)
Inventor
Tadao Kaji
Tsuneaki Kamei
Keiji Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2545513A1 publication Critical patent/DE2545513A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/036—Diffusion, nonselective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Landscapes

  • Element Separation (AREA)
DE19752545513 1974-10-18 1975-10-10 Halbleitervorrichtung und verfahren zu deren herstellung Ceased DE2545513A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49119357A JPS5146083A (en) 1974-10-18 1974-10-18 Handotaisochino seizohoho

Publications (1)

Publication Number Publication Date
DE2545513A1 true DE2545513A1 (de) 1976-04-29

Family

ID=14759476

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752545513 Ceased DE2545513A1 (de) 1974-10-18 1975-10-10 Halbleitervorrichtung und verfahren zu deren herstellung

Country Status (4)

Country Link
US (1) US3997378A (https=)
JP (1) JPS5146083A (https=)
DE (1) DE2545513A1 (https=)
GB (1) GB1501483A (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104090A (en) * 1977-02-24 1978-08-01 International Business Machines Corporation Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation
US4219369A (en) * 1977-09-30 1980-08-26 Hitachi, Ltd. Method of making semiconductor integrated circuit device
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4275286A (en) * 1978-12-04 1981-06-23 Hughes Aircraft Company Process and mask for ion beam etching of fine patterns
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
US4290843A (en) * 1980-02-19 1981-09-22 Texas Instruments Incorporated Epitaxial growth of magnetic memory film on implanted substrate
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
IT1200725B (it) * 1985-08-28 1989-01-27 Sgs Microelettronica Spa Struttura di isolamento in dispositivi mos e procedimento di preparazione della stessa
JP2641781B2 (ja) * 1990-02-23 1997-08-20 シャープ株式会社 半導体素子分離領域の形成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3135638A (en) * 1960-10-27 1964-06-02 Hughes Aircraft Co Photochemical semiconductor mesa formation
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3447984A (en) * 1965-06-24 1969-06-03 Ibm Method for forming sharply defined apertures in an insulating layer
US3537925A (en) * 1967-03-14 1970-11-03 Gen Electric Method of forming a fine line apertured film
FR1527898A (fr) * 1967-03-16 1968-06-07 Radiotechnique Coprim Rtc Agencement de dispositifs semi-conducteurs portés par un support commun et son procédé de fabrication
GB1206308A (en) * 1967-11-22 1970-09-23 Sony Corp Method of making semiconductor wafer
US3617822A (en) * 1967-12-05 1971-11-02 Sony Corp Semiconductor integrated circuit
US3947299A (en) * 1971-05-22 1976-03-30 U.S. Philips Corporation Method of manufacturing semiconductor devices
US3861968A (en) * 1972-06-19 1975-01-21 Ibm Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
US3954522A (en) * 1973-06-28 1976-05-04 Motorola, Inc. Integrated circuit process

Also Published As

Publication number Publication date
JPS5146083A (en) 1976-04-20
US3997378A (en) 1976-12-14
GB1501483A (en) 1978-02-15
JPS5342638B2 (https=) 1978-11-13

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING. SCHUEBE

8131 Rejection