DE2543539A1 - Schaltungsanordnung zur rekonstruktion eines digitalen eingangssignals - Google Patents

Schaltungsanordnung zur rekonstruktion eines digitalen eingangssignals

Info

Publication number
DE2543539A1
DE2543539A1 DE19752543539 DE2543539A DE2543539A1 DE 2543539 A1 DE2543539 A1 DE 2543539A1 DE 19752543539 DE19752543539 DE 19752543539 DE 2543539 A DE2543539 A DE 2543539A DE 2543539 A1 DE2543539 A1 DE 2543539A1
Authority
DE
Germany
Prior art keywords
signal
clock signal
circuit arrangement
clock
delay line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19752543539
Other languages
German (de)
English (en)
Inventor
William N Waggener
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Weston Instruments Inc
Original Assignee
Weston Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Weston Instruments Inc filed Critical Weston Instruments Inc
Publication of DE2543539A1 publication Critical patent/DE2543539A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0262—Arrangements for detecting the data rate of an incoming signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Manipulation Of Pulses (AREA)
DE19752543539 1974-10-07 1975-09-30 Schaltungsanordnung zur rekonstruktion eines digitalen eingangssignals Withdrawn DE2543539A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US512990A US3908115A (en) 1974-10-07 1974-10-07 Adaptively tuned data receiver

Publications (1)

Publication Number Publication Date
DE2543539A1 true DE2543539A1 (de) 1976-05-13

Family

ID=24041463

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752543539 Withdrawn DE2543539A1 (de) 1974-10-07 1975-09-30 Schaltungsanordnung zur rekonstruktion eines digitalen eingangssignals

Country Status (6)

Country Link
US (1) US3908115A (OSRAM)
JP (1) JPS5164359A (OSRAM)
DE (1) DE2543539A1 (OSRAM)
FR (1) FR2287809A1 (OSRAM)
GB (1) GB1528483A (OSRAM)
IT (1) IT1043028B (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2908588A1 (de) * 1978-03-10 1979-09-20 Cit Alcatel Schaltungsanordnung zur automatischen entzerrung in binaeren uebertragungsstrecken

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51108757A (OSRAM) * 1975-03-20 1976-09-27 Mitsubishi Electric Corp
FR2336005A1 (fr) * 1975-12-18 1977-07-15 Ibm France Filtre numerique auto-adaptatif
FI77955C (fi) * 1978-03-22 1989-05-10 Mitsubishi Electric Corp Anpassningsfilter.
JPS5665530A (en) * 1979-10-31 1981-06-03 Sony Corp Pll circuit
USRE31720E (en) * 1979-08-30 1984-10-30 Deltalab Research, Inc. Digital encoding circuitry
US4254502A (en) * 1979-08-30 1981-03-03 Deltalab Research, Inc. Digital encoding circuitry
US4320345A (en) * 1980-04-28 1982-03-16 Sangamo Weston, Inc. Adaptive differential PSK demodulator
US4389622A (en) * 1981-09-28 1983-06-21 Honeywell Inc. System for preventing transient induced errors in phase locked loop
US4419760A (en) * 1982-01-29 1983-12-06 Motorola Inc. Augmented phase-locked loop for very wide range acquisition and method therefor
US4556866A (en) * 1983-03-16 1985-12-03 Honeywell Inc. Power line carrier FSK data system
US4706263A (en) * 1983-11-07 1987-11-10 Hughes Aircraft Company Data communications receiver operable in highly stressed environments
USH2069H1 (en) 1984-12-21 2003-07-01 The United States Of America As Represented By The Secretary Of The Navy Signal processor
US4654811A (en) * 1985-02-12 1987-03-31 Allied Corporation Adaptive filter for aircraft navigation receiver
CA1253619A (en) * 1985-04-22 1989-05-02 Sony Corporation Apparatus for reproducing a digital signal
US4694415A (en) * 1985-05-01 1987-09-15 Westinghouse Electric Corp. Adaptive digital filter for analog input signals
EP0228646A3 (en) * 1985-12-20 1987-10-14 Hitachi, Ltd. A signal processing apparatus for disc memory devices
US4744094A (en) * 1986-12-12 1988-05-10 Zenith Electronics Corporation BPSK demodulator with D type flip/flop
US4837781A (en) * 1987-04-07 1989-06-06 Gigabit Logic, Inc. Phase locked loop clock synchronizer and signal detector
US5150317A (en) * 1989-01-11 1992-09-22 The Boeing Company Adaptive digital filter which is responsive to the rate of change of an input signal
US5457718A (en) * 1992-03-02 1995-10-10 International Business Machines Corporation Compact phase recovery scheme using digital circuits
JP3366032B2 (ja) * 1992-12-14 2003-01-14 パイオニア株式会社 キャリア同期用ｐｌｌ回路
US6285722B1 (en) * 1997-12-05 2001-09-04 Telcordia Technologies, Inc. Method and apparatus for variable bit rate clock recovery
US6249556B1 (en) * 1998-05-27 2001-06-19 Intel Corporation Dynamic thresholding for input receivers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518547A (en) * 1966-06-14 1970-06-30 Ibm Digital communication system employing multiplex transmission of maximal length binary sequences
US3694752A (en) * 1971-03-18 1972-09-26 North American Rockwell High speed transmission receiver utilizing fine receiver timing and carrier phase recovery
US3736530A (en) * 1972-02-22 1973-05-29 Bell Telephone Labor Inc Adjustable equalizer control apparatus
US3846708A (en) * 1973-03-15 1974-11-05 Bell Telephone Labor Inc Digital demodulation of frequency-shift keyed data signals

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2908588A1 (de) * 1978-03-10 1979-09-20 Cit Alcatel Schaltungsanordnung zur automatischen entzerrung in binaeren uebertragungsstrecken

Also Published As

Publication number Publication date
US3908115A (en) 1975-09-23
FR2287809A1 (fr) 1976-05-07
IT1043028B (it) 1980-02-20
JPS5164359A (OSRAM) 1976-06-03
GB1528483A (en) 1978-10-11
FR2287809B1 (OSRAM) 1979-06-15

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Legal Events

Date Code Title Description
8141 Disposal/no request for examination