DE2526722A1 - Stapel-speicher-organisation mit ladungskopplung - Google Patents

Stapel-speicher-organisation mit ladungskopplung

Info

Publication number
DE2526722A1
DE2526722A1 DE19752526722 DE2526722A DE2526722A1 DE 2526722 A1 DE2526722 A1 DE 2526722A1 DE 19752526722 DE19752526722 DE 19752526722 DE 2526722 A DE2526722 A DE 2526722A DE 2526722 A1 DE2526722 A1 DE 2526722A1
Authority
DE
Germany
Prior art keywords
input
gate
register
output
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19752526722
Other languages
German (de)
English (en)
Inventor
Deepak Kumar Goyal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of DE2526722A1 publication Critical patent/DE2526722A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
DE19752526722 1974-06-21 1975-06-14 Stapel-speicher-organisation mit ladungskopplung Withdrawn DE2526722A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/481,728 US3942163A (en) 1974-06-21 1974-06-21 CCD stack memory organization

Publications (1)

Publication Number Publication Date
DE2526722A1 true DE2526722A1 (de) 1976-01-08

Family

ID=23913144

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752526722 Withdrawn DE2526722A1 (de) 1974-06-21 1975-06-14 Stapel-speicher-organisation mit ladungskopplung

Country Status (8)

Country Link
US (1) US3942163A (enExample)
JP (1) JPS519537A (enExample)
BR (1) BR7503482A (enExample)
DE (1) DE2526722A1 (enExample)
FR (1) FR2275849A1 (enExample)
GB (1) GB1475211A (enExample)
IN (1) IN143604B (enExample)
NL (1) NL7506193A (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814749B2 (ja) * 1976-04-15 1983-03-22 富士通株式会社 電荷転送装置
CA1101993A (en) * 1976-04-15 1981-05-26 Kunihiro Tanikawa Charge coupled device
JPS5747490Y2 (enExample) * 1976-07-14 1982-10-19
US4130894A (en) * 1977-11-21 1978-12-19 International Business Machines Corporation Loop organized serial-parallel-serial memory storage system
NL7713707A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met variabele ingang en vaste uitgang.
US4312051A (en) * 1978-10-30 1982-01-19 Phillips Petroleum Company Data display
US4296484A (en) * 1978-10-30 1981-10-20 Phillips Petroleum Company Data display system
US4313159A (en) * 1979-02-21 1982-01-26 Massachusetts Institute Of Technology Data storage and access apparatus
US4482970A (en) * 1981-11-06 1984-11-13 Grumman Aerospace Corporation Boolean filtering method and apparatus
US4827445A (en) * 1982-02-18 1989-05-02 University Of North Carolina Image buffer having logic-enhanced pixel memory cells and method for setting values therein
US4590465A (en) * 1982-02-18 1986-05-20 Henry Fuchs Graphics display system using logic-enhanced pixel memory cells
US4783649A (en) * 1982-08-13 1988-11-08 University Of North Carolina VLSI graphics display image buffer using logic enhanced pixel memory cells
JPS61289448A (ja) * 1985-06-18 1986-12-19 Mitsubishi Electric Corp バツフア記憶装置
US4813015A (en) * 1986-03-12 1989-03-14 Advanced Micro Devices, Inc. Fracturable x-y storage array using a ram cell with bidirectional shift
US4709381A (en) * 1986-03-19 1987-11-24 Westinghouse Electric Corp. CCD focal plane array convolver
US4899307A (en) * 1987-04-10 1990-02-06 Tandem Computers Incorporated Stack with unary encoded stack pointer
US5023828A (en) * 1988-07-20 1991-06-11 Digital Equipment Corporation Microinstruction addressing in high-speed CPU
US5818821A (en) * 1994-12-30 1998-10-06 Intelogis, Inc. Universal lan power line carrier repeater system and method
US7983373B2 (en) * 2007-02-07 2011-07-19 Vintomie Networks B.V., Llc Clock distribution for 10GBase-T analog front end

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3772658A (en) * 1971-02-05 1973-11-13 Us Army Electronic memory having a page swapping capability
US3763480A (en) * 1971-10-12 1973-10-02 Rca Corp Digital and analog data handling devices

Also Published As

Publication number Publication date
BR7503482A (pt) 1976-07-06
GB1475211A (en) 1977-06-01
IN143604B (enExample) 1977-12-31
FR2275849A1 (fr) 1976-01-16
US3942163A (en) 1976-03-02
NL7506193A (nl) 1975-12-23
JPS519537A (enExample) 1976-01-26

Similar Documents

Publication Publication Date Title
DE2526722A1 (de) Stapel-speicher-organisation mit ladungskopplung
DE2604449C3 (de) Analog-Digital-Umsetzer
DE2828726C2 (de) Monolithische integrierte Schaltungsstruktur mit einer Speichervorrichtung
DE3741878A1 (de) Variable verzoegerungsschaltung
DE2748536C2 (enExample)
DE3742514C2 (enExample)
DE2063313B2 (de) Verfahren zum kontinuierlichen Ein- oder Auslesen eines Speichers
DE69520933T2 (de) Festkörperbildaufnahmevorrichtung und Verfahren zu ihrem Betrieb
DE2431782A1 (de) Datenverarbeitungsanordnung mit ladungsuebertragungsbauelementen
DE2531382A1 (de) Halbleiterspeicher zum blockorientierten lesen und schreiben
DE2706807C2 (de) Einrichtung und Verfahren zum Verarbeiten von Information in Form digitaler Signale
DE1574499B2 (de) Speicheranordnung für binare Daten unter Verwendung einer ge schlossenen Datenumlaufschleife
DE2357007B2 (de) Schieberegisterspeicher mit mehrdimensionaler dynam ischer Ordnung
DE2325922C2 (de) Aus Schieberegistern aufgebaute Speicheranordnung mit dynamischer Umordnung
EP0013697A1 (de) Auffrischung benötigendes seitenorganisiertes Speichersystem
DE2558287C2 (de) Informationsspeicher
DE2629329A1 (de) Ccd-schieberegister
DE2629263A1 (de) Ccd-schieberegister
DE2543023C3 (de) Speicheranordnung mit Bausteinen aus Ladungsverschiebespeichern
EP0006466B1 (de) Ladungsverschiebungseinrichtung und Verfahren zum Betrieb dieser Einrichtung
DE2537194A1 (de) Stapelspeicher in ladungs-kopplungs-technik sowie verfahren zu seiner auffrischung
DE1285218B (de) Datenverarbeitungsanlage
EP0012841A2 (de) Spalten- und zeilenadressierbarer Speicher in Serien-Parallel-Serien-Konfiguration
DE2025857A1 (de) Datenspeicherschaltung in der Form einer zweiphasigen Schieberegisterzelle sehr hoher Arbeitsgeschwindigkeit und geringer Leistungsaufnahme
DE69021446T2 (de) Programmierbares Binärsignal-Verzögerungsverfahren und Anwendung auf ein Fehlerkorrigierkode-Verfahren.

Legal Events

Date Code Title Description
8141 Disposal/no request for examination