DE2504288A1 - Binaeraddierer - Google Patents

Binaeraddierer

Info

Publication number
DE2504288A1
DE2504288A1 DE19752504288 DE2504288A DE2504288A1 DE 2504288 A1 DE2504288 A1 DE 2504288A1 DE 19752504288 DE19752504288 DE 19752504288 DE 2504288 A DE2504288 A DE 2504288A DE 2504288 A1 DE2504288 A1 DE 2504288A1
Authority
DE
Germany
Prior art keywords
circuit
logic
signal line
circuits
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19752504288
Other languages
German (de)
English (en)
Inventor
Murray J Haims
Hsieh Tung Hao
@@ Lebizay Gerald
@@ Weiss Alfred
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2504288A1 publication Critical patent/DE2504288A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
DE19752504288 1974-03-07 1975-02-01 Binaeraddierer Pending DE2504288A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US449133A US3902055A (en) 1974-03-07 1974-03-07 Binary adder circuit

Publications (1)

Publication Number Publication Date
DE2504288A1 true DE2504288A1 (de) 1975-09-11

Family

ID=23782991

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752504288 Pending DE2504288A1 (de) 1974-03-07 1975-02-01 Binaeraddierer

Country Status (5)

Country Link
US (1) US3902055A (enExample)
JP (1) JPS50120938A (enExample)
DE (1) DE2504288A1 (enExample)
FR (1) FR2263555B1 (enExample)
GB (1) GB1466366A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638449A (en) * 1983-06-15 1987-01-20 International Business Machines Corporation Multiplier architecture

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3612847A (en) * 1964-04-03 1971-10-12 Saint Gobain Electrical apparatus and method for adding binary numbers
JPS5013068B1 (enExample) * 1970-07-31 1975-05-16
US3717755A (en) * 1971-05-21 1973-02-20 Bell Telephone Labor Inc Parallel adder using a carry propagation bus
US3728532A (en) * 1972-01-21 1973-04-17 Rca Corp Carry skip-ahead network
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder

Also Published As

Publication number Publication date
FR2263555A1 (enExample) 1975-10-03
GB1466366A (en) 1977-03-09
US3902055A (en) 1975-08-26
JPS50120938A (enExample) 1975-09-22
FR2263555B1 (enExample) 1977-11-18

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