DE2326005A1 - Verfahren zur bildung von halbleitervorrichtungen - Google Patents

Verfahren zur bildung von halbleitervorrichtungen

Info

Publication number
DE2326005A1
DE2326005A1 DE2326005A DE2326005A DE2326005A1 DE 2326005 A1 DE2326005 A1 DE 2326005A1 DE 2326005 A DE2326005 A DE 2326005A DE 2326005 A DE2326005 A DE 2326005A DE 2326005 A1 DE2326005 A1 DE 2326005A1
Authority
DE
Germany
Prior art keywords
layer
forming
electrode
active semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2326005A
Other languages
German (de)
English (en)
Inventor
Ronald G Neallle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Energy Conversion Devices Inc
Original Assignee
Energy Conversion Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Energy Conversion Devices Inc filed Critical Energy Conversion Devices Inc
Publication of DE2326005A1 publication Critical patent/DE2326005A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/231Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/021Formation of switching materials, e.g. deposition of layers
    • H10N70/026Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/061Shaping switching materials
    • H10N70/063Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/826Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/017Clean surfaces
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/158Sputtering

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Static Random-Access Memory (AREA)
DE2326005A 1972-06-21 1973-05-22 Verfahren zur bildung von halbleitervorrichtungen Pending DE2326005A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00264937A US3816197A (en) 1969-10-17 1972-06-21 Film deposited semiconductor devices

Publications (1)

Publication Number Publication Date
DE2326005A1 true DE2326005A1 (de) 1974-01-17

Family

ID=23008278

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2326005A Pending DE2326005A1 (de) 1972-06-21 1973-05-22 Verfahren zur bildung von halbleitervorrichtungen

Country Status (11)

Country Link
US (1) US3816197A (en:Method)
JP (1) JPS4964384A (en:Method)
AU (1) AU5680173A (en:Method)
BE (1) BE800712A (en:Method)
CA (1) CA976668A (en:Method)
DD (1) DD104875A5 (en:Method)
DE (1) DE2326005A1 (en:Method)
FR (1) FR2189872B3 (en:Method)
IL (1) IL42260A0 (en:Method)
IT (1) IT988915B (en:Method)
NL (1) NL7307471A (en:Method)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956042A (en) * 1974-11-07 1976-05-11 Xerox Corporation Selective etchants for thin film devices
US4833100A (en) * 1985-12-12 1989-05-23 Kozo Iizuka, Director-General Of Agency Of Industrial Science And Technology Method for producing a silicon thin film by MBE using silicon beam precleaning
DE3805877A1 (de) * 1988-02-25 1989-08-31 Roland Man Druckmasch Adressiervorrichtung fuer produkte, insbesondere fuer falzprodukte

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3326729A (en) * 1963-08-20 1967-06-20 Hughes Aircraft Co Epitaxial method for the production of microcircuit components
US3271591A (en) * 1963-09-20 1966-09-06 Energy Conversion Devices Inc Symmetrical current controlling device
US3597297A (en) * 1968-06-25 1971-08-03 Minnesota Mining & Mfg Synthetic turf material and method of making same
JPS5522945A (en) * 1978-08-09 1980-02-19 Hitachi Ltd Ink jet recording device

Also Published As

Publication number Publication date
FR2189872A1 (en:Method) 1974-01-25
JPS4964384A (en:Method) 1974-06-21
FR2189872B3 (en:Method) 1976-06-11
NL7307471A (en:Method) 1973-12-27
CA976668A (en) 1975-10-21
DD104875A5 (en:Method) 1974-03-20
AU5680173A (en) 1974-12-12
IT988915B (it) 1975-04-30
BE800712A (fr) 1973-10-01
US3816197A (en) 1974-06-11
IL42260A0 (en) 1973-07-30

Similar Documents

Publication Publication Date Title
DE2822264C2 (de) Halbleiter-Speicherelement
DE69611540T2 (de) Erzeugung von kontakten für halbleiterstrahlungsdetektoren und bildaufnahmevorrichtungen
DE2945533C2 (de) Verfahren zur Herstellung eines Verdrahtungssystems
DE2217538C3 (de) Verfahren zur Herstellung von Zwischenverbindungen in einer Halbleiteranordnung
DE4230338B4 (de) Verfahren zur Herstellung von Solarzellen aus amorphem Silizium mittels Naßätzen von Löchern oder Gräben durch Rückseitenelektroden und amorphes Silizium
DE1930669C2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung
DE3117950A1 (de) Planare duennfilmtransistoren, transistoranordnungen und verfahren zu ihrer herstellung
DE3906018A1 (de) Verfahren zum einkapseln von leitern
DE3874785T2 (de) Duennfilmkondensator.
DE3886115T2 (de) Verfahren zum Anbringen dünner Schichten aus oxidischem supraleitendem Material.
DE3038773C2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltungsanordnung mit MOS-Transistoren und mit spannungsunabhängigen Kondensatoren
DE3312053C2 (de) Verfahren zum Verhindern von Kurz- oder Nebenschlüssen in einer großflächigen Dünnschicht-Solarzelle
DE3041839A1 (de) Verfahren zur bildung eines fuennfilmschemas
DE2556038C2 (de) Verfahren zur Herstellung von Feldeffekttransistoren mit Schottky-Gate für sehr hohe Frequenzen
DE3217026A1 (de) Halbleitervorrichtung
DE3543937C2 (en:Method)
DE10039710B4 (de) Verfahren zur Herstellung passiver Bauelemente auf einem Halbleitersubstrat
DE2336908B2 (de) Integrierte Halbleiteranordnung mit Mehrlagen-Metallisierung-
DE2326005A1 (de) Verfahren zur bildung von halbleitervorrichtungen
DE69223118T2 (de) Dünnschicht-Transistor-Panel und dessen Herstellungsmethode
DE3714920C1 (de) Verfahren zur Herstellung einer Duennschicht-Solarzellenanordnung
DE19515591C2 (de) Anordnung zur Formierung von vertikalen Kontakten zwischen zwei Leitbahnen in mikroelektronischen Schaltungen mit mehr als zwei Metallisierungslagen
DE3409387C2 (de) Halbleitervorrichtung
DE1564136C3 (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE19710375C2 (de) Verfahren zum Herstellen von räumlich strukturierten Bauteilen