DE2114772A1 - Verfahren zum epitaktischen Aufwachsen von Verbindungshalbleitern aus der Dampfphase - Google Patents

Verfahren zum epitaktischen Aufwachsen von Verbindungshalbleitern aus der Dampfphase

Info

Publication number
DE2114772A1
DE2114772A1 DE19712114772 DE2114772A DE2114772A1 DE 2114772 A1 DE2114772 A1 DE 2114772A1 DE 19712114772 DE19712114772 DE 19712114772 DE 2114772 A DE2114772 A DE 2114772A DE 2114772 A1 DE2114772 A1 DE 2114772A1
Authority
DE
Germany
Prior art keywords
layer
epitaxial
vapor phase
epitaxial growth
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712114772
Other languages
German (de)
English (en)
Inventor
Yuichi Kokubunji; Ogirima Masahiko Shinjuku Tokio; Kasano Hiroyuki Akishima; Kurata Kazuhiro Hachioji; Ono (Japan). MP
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2114772A1 publication Critical patent/DE2114772A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
    • H10P14/2911—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3418—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/916—Autodoping control or utilization
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation
DE19712114772 1970-03-27 1971-03-26 Verfahren zum epitaktischen Aufwachsen von Verbindungshalbleitern aus der Dampfphase Pending DE2114772A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP45025276A JPS4929099B1 (enExample) 1970-03-27 1970-03-27

Publications (1)

Publication Number Publication Date
DE2114772A1 true DE2114772A1 (de) 1971-10-28

Family

ID=12161482

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712114772 Pending DE2114772A1 (de) 1970-03-27 1971-03-26 Verfahren zum epitaktischen Aufwachsen von Verbindungshalbleitern aus der Dampfphase

Country Status (3)

Country Link
US (1) US3769104A (enExample)
JP (1) JPS4929099B1 (enExample)
DE (1) DE2114772A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4000020A (en) * 1973-04-30 1976-12-28 Texas Instruments Incorporated Vapor epitaxial method for depositing gallium arsenide phosphide on germanium and silicon substrate wafers
DE2506457C3 (de) * 1975-02-15 1980-01-24 S.A. Metallurgie Hoboken-Overpelt N.V., Bruessel Verfahren zur Herstellung einer silikatischen Abdeckschicht auf einer Halbleiterscheibe öder auf einer auf ihr befindlichen Schicht
US3960620A (en) * 1975-04-21 1976-06-01 Rca Corporation Method of making a transmission mode semiconductor photocathode
DE2601652C3 (de) * 1976-01-17 1979-11-08 Metallurgie Hoboken-Overpelt, Bruessel Verfahren zur epitaxialen Abscheidung einer Am. Bv Halbleiterschicht auf einem Germaniumsubstrat mit einer (100)-Orientierong
JPS5350672A (en) * 1976-10-19 1978-05-09 Mitsubishi Electric Corp Production of substrate for semiconductor device
US4582561A (en) * 1979-01-25 1986-04-15 Sharp Kabushiki Kaisha Method for making a silicon carbide substrate
EP0030798B1 (en) * 1979-12-17 1983-12-28 Hughes Aircraft Company Low temperature process for depositing oxide layers by photochemical vapor deposition
US4517220A (en) * 1983-08-15 1985-05-14 Motorola, Inc. Deposition and diffusion source control means and method
US4662956A (en) * 1985-04-01 1987-05-05 Motorola, Inc. Method for prevention of autodoping of epitaxial layers
US4687682A (en) * 1986-05-02 1987-08-18 American Telephone And Telegraph Company, At&T Technologies, Inc. Back sealing of silicon wafers
US5225235A (en) * 1987-05-18 1993-07-06 Osaka Titanium Co., Ltd. Semiconductor wafer and manufacturing method therefor
US4925809A (en) * 1987-05-23 1990-05-15 Osaka Titanium Co., Ltd. Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor
JP3454033B2 (ja) * 1996-08-19 2003-10-06 信越半導体株式会社 シリコンウェーハおよびその製造方法
US6140255A (en) * 1998-12-15 2000-10-31 Advanced Micro Devices, Inc. Method for depositing silicon nitride using low temperatures
SG114574A1 (en) * 2002-09-25 2005-09-28 Siltronic Singapore Pte Ltd Two layer lto backside seal for a wafer
US7205216B2 (en) * 2004-07-29 2007-04-17 International Business Machines Corporation Modification of electrical properties for semiconductor wafers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3296040A (en) * 1962-08-17 1967-01-03 Fairchild Camera Instr Co Epitaxially growing layers of semiconductor through openings in oxide mask
DE1544264C3 (de) * 1965-07-01 1974-10-24 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen von Halbleiterschichten durch Abscheiden aus der Gasphase
US3663319A (en) * 1968-11-20 1972-05-16 Gen Motors Corp Masking to prevent autodoping of epitaxial deposits

Also Published As

Publication number Publication date
US3769104A (en) 1973-10-30
JPS4929099B1 (enExample) 1974-08-01

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