DE2109895C3 - Schaltungsanordnung zur identischen Zeitverzögerung zweier Signale in entgegengesetzter Richtung - Google Patents

Schaltungsanordnung zur identischen Zeitverzögerung zweier Signale in entgegengesetzter Richtung

Info

Publication number
DE2109895C3
DE2109895C3 DE19712109895 DE2109895A DE2109895C3 DE 2109895 C3 DE2109895 C3 DE 2109895C3 DE 19712109895 DE19712109895 DE 19712109895 DE 2109895 A DE2109895 A DE 2109895A DE 2109895 C3 DE2109895 C3 DE 2109895C3
Authority
DE
Germany
Prior art keywords
signal
circuit
input signal
output
circuit arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19712109895
Other languages
German (de)
English (en)
Other versions
DE2109895B2 (de
DE2109895A1 (de
Inventor
Hiro Portland Oreg. Moriyasu (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of DE2109895A1 publication Critical patent/DE2109895A1/de
Publication of DE2109895B2 publication Critical patent/DE2109895B2/de
Application granted granted Critical
Publication of DE2109895C3 publication Critical patent/DE2109895C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/20—Cathode-ray oscilloscopes
    • G01R13/22—Circuits therefor
    • G01R13/32—Circuits for displaying non-recurrent functions such as transients; Circuits for triggering; Circuits for synchronisation; Circuits for time-base expansion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
DE19712109895 1970-03-02 1971-03-02 Schaltungsanordnung zur identischen Zeitverzögerung zweier Signale in entgegengesetzter Richtung Expired DE2109895C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1556770A 1970-03-02 1970-03-02

Publications (3)

Publication Number Publication Date
DE2109895A1 DE2109895A1 (de) 1971-09-23
DE2109895B2 DE2109895B2 (de) 1978-06-22
DE2109895C3 true DE2109895C3 (de) 1979-02-15

Family

ID=21772176

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712109895 Expired DE2109895C3 (de) 1970-03-02 1971-03-02 Schaltungsanordnung zur identischen Zeitverzögerung zweier Signale in entgegengesetzter Richtung

Country Status (5)

Country Link
JP (1) JPS5213073B1 (enExample)
DE (1) DE2109895C3 (enExample)
FR (1) FR2081625B1 (enExample)
GB (1) GB1300649A (enExample)
NL (1) NL7102414A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993867A (en) * 1974-10-15 1976-11-23 Motorola, Inc. Digital single signal line full duplex method and apparatus
USRE30111E (en) 1974-10-15 1979-10-09 Motorola, Inc. Digital single signal line full duplex method and apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3168A (en) * 1843-07-12 terry
US2629024A (en) * 1950-12-29 1953-02-17 Bell Telephone Labor Inc Unbalanced-to-ground two-to-fourwire connection

Also Published As

Publication number Publication date
JPS5213073B1 (enExample) 1977-04-12
DE2109895B2 (de) 1978-06-22
FR2081625A1 (enExample) 1971-12-10
GB1300649A (en) 1972-12-20
NL7102414A (enExample) 1971-09-06
DE2109895A1 (de) 1971-09-23
FR2081625B1 (enExample) 1976-09-03

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee