DE2042586C3 - Halbleitereinrichtung mit mindestens einem Feldeffekttransistor - Google Patents

Halbleitereinrichtung mit mindestens einem Feldeffekttransistor

Info

Publication number
DE2042586C3
DE2042586C3 DE2042586A DE2042586A DE2042586C3 DE 2042586 C3 DE2042586 C3 DE 2042586C3 DE 2042586 A DE2042586 A DE 2042586A DE 2042586 A DE2042586 A DE 2042586A DE 2042586 C3 DE2042586 C3 DE 2042586C3
Authority
DE
Germany
Prior art keywords
carrier body
semiconductor device
electrode
zone
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2042586A
Other languages
German (de)
English (en)
Other versions
DE2042586B2 (de
DE2042586A1 (de
Inventor
Hiroto Kawagoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2042586A1 publication Critical patent/DE2042586A1/de
Publication of DE2042586B2 publication Critical patent/DE2042586B2/de
Application granted granted Critical
Publication of DE2042586C3 publication Critical patent/DE2042586C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
DE2042586A 1969-08-27 1970-08-27 Halbleitereinrichtung mit mindestens einem Feldeffekttransistor Expired DE2042586C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP44067192A JPS4819113B1 (OSRAM) 1969-08-27 1969-08-27

Publications (3)

Publication Number Publication Date
DE2042586A1 DE2042586A1 (de) 1971-03-11
DE2042586B2 DE2042586B2 (de) 1978-11-16
DE2042586C3 true DE2042586C3 (de) 1984-01-26

Family

ID=13337780

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2042586A Expired DE2042586C3 (de) 1969-08-27 1970-08-27 Halbleitereinrichtung mit mindestens einem Feldeffekttransistor

Country Status (4)

Country Link
US (1) US3688165A (OSRAM)
JP (1) JPS4819113B1 (OSRAM)
DE (1) DE2042586C3 (OSRAM)
GB (1) GB1318444A (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4076558A (en) * 1977-01-31 1978-02-28 International Business Machines Corporation Method of high current ion implantation and charge reduction by simultaneous kerf implant
JPS58157151A (ja) * 1982-03-15 1983-09-19 Mitsubishi Electric Corp 半導体集積回路装置
US5936454A (en) * 1993-06-01 1999-08-10 Motorola, Inc. Lateral bipolar transistor operating with independent base and gate biasing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1043472B (de) * 1956-02-06 1958-11-13 Siemens Ag Halbleiterbauelement zur Stromstabilisierung
NL267390A (OSRAM) * 1960-09-28
US3197681A (en) * 1961-09-29 1965-07-27 Texas Instruments Inc Semiconductor devices with heavily doped region to prevent surface inversion
US3284723A (en) * 1962-07-02 1966-11-08 Westinghouse Electric Corp Oscillatory circuit and monolithic semiconductor device therefor
BE637064A (OSRAM) * 1962-09-07 Rca Corp
GB993388A (en) * 1964-02-05 1965-05-26 Standard Telephones Cables Ltd Improvements in or relating to semiconductor devices
US3305708A (en) * 1964-11-25 1967-02-21 Rca Corp Insulated-gate field-effect semiconductor device
DE1514495C3 (de) * 1965-07-01 1974-10-17 Siemens Ag, 1000 Berlin Und 8000 Muenchen Halbleiteranordnung
GB1217880A (en) * 1967-10-13 1970-12-31 Rca Corp Lateral transistor with auxiliary control electrode
NL6715013A (OSRAM) * 1967-11-04 1969-05-06
US3570112A (en) * 1967-12-01 1971-03-16 Nat Defence Canada Radiation hardening of insulated gate field effect transistors
US3573509A (en) * 1968-09-09 1971-04-06 Texas Instruments Inc Device for reducing bipolar effects in mos integrated circuits

Also Published As

Publication number Publication date
DE2042586B2 (de) 1978-11-16
JPS4819113B1 (OSRAM) 1973-06-11
DE2042586A1 (de) 1971-03-11
US3688165A (en) 1972-08-29
GB1318444A (en) 1973-05-31

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Legal Events

Date Code Title Description
8228 New agent

Free format text: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING., PAT.-ANW., 8000 MUENCHEN

8281 Inventor (new situation)

Free format text: TOMINAGA, YOSHIO KAWAGOE, HIROTO TERANISHI, YUICHI, KODAIRA, TOKYO, JP

C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee