GB993388A - Improvements in or relating to semiconductor devices - Google Patents

Improvements in or relating to semiconductor devices

Info

Publication number
GB993388A
GB993388A GB493164A GB493164A GB993388A GB 993388 A GB993388 A GB 993388A GB 493164 A GB493164 A GB 493164A GB 493164 A GB493164 A GB 493164A GB 993388 A GB993388 A GB 993388A
Authority
GB
United Kingdom
Prior art keywords
slice
layer
type
auxiliary
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB493164A
Inventor
Fritz Gunter Adam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB493164A priority Critical patent/GB993388A/en
Priority to DE19651268746 priority patent/DE1268746C2/en
Publication of GB993388A publication Critical patent/GB993388A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B27/00—Photographic printing apparatus
    • G03B27/32—Projection printing apparatus, e.g. enlarger, copying camera
    • G03B27/52—Details
    • G03B27/53—Automatic registration or positioning of originals with respect to each other or the photosensitive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

993,388. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. Feb. 5, 1964, No. 4931/64. Heading H1K. In a method of manufacturing a plurality of semi-conductor devices in a slice of semi-conductor material by diffusion of impurities through a mask, the mask is provided with apertures for producing an array of discrete devices and for producing an array of areas to form an auxiliary pattern of structures separate from the devices, on which resistivity measurements are made. A plurality of highpower transistors are manufactured by oxidizing the surface of a slice of N-type silicon which is then coated with a photoresist and exposed to the pattern shown in Fig. 2. The photoresist is developed and the oxide layer is etched to produce windows corresponding to the shaded areas 3, 4 and 5. Boron is applied to the surface of the slice which is then heated to " drive-in " the impurity to form P-type base regions corresponding to areas 3 and an auxiliary pattern 4, 5 of P-type areas. The exposed surface of the slice is re-oxidized during the diffusion but this fresh layer of oxide is thinner than the remaining layer and can be seen due to the multiple interference of light reflected between the surfaces of the layer. A second exposure mask, see Fig. 5, is aligned using the T-shaped stripes visible on the slice, and corresponding windows are etched in the oxide layer. A four-point probe is applied to the diffused auxiliary layer exposed by area 11 to measure the surface resistivity of the layer. This is repeated at several places across the slice and any slices which show a variation in resistivity are discarded. If the resistivity is uniform but of an unsuitable value the slice may be reprocessed either by heating to continue the diffusion or by depositing more impurity and then heating. Phosphorus is then diffused into suitable slices to form N-type areas, the patterns 9 forming the emitter regions of the transistors. The oxide layer is again reformed, the pattern shown in Fig. 9 is aligned, again using the T-shaped stripes, and corresponding windows are etched. The four-point probe is used to measure the surface resistivity of the N-type diffused layer by applying it to the auxiliary stripes. The area 10, Fig. 5, provides a narrow N-type region 13, Fig. 15, across certain of the non-T- shaped P-type stripes 7 diffused into the slice and the four-point probe can be applied to measure the resistance of the P-type channel passing between substrate 1 and region 13 to give an indication of the base resistance of the transistors, and unsuitable slices can be discarded or reprocessed. Aluminium is vapour deposited over the surface of the slice, masked and etched, and then heated to alloy the aluminium and produce the required emitter and base contacts. The slice is then scribed along the auxiliary stripes and flexed to break it into individual transistors. The use of the invention for low and medium power transistors is also described, the differences being in the geometry of the devices and slightly different patterns of the auxiliary structures (Figs. 21 and 26, not shown).
GB493164A 1964-02-05 1964-02-05 Improvements in or relating to semiconductor devices Expired GB993388A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB493164A GB993388A (en) 1964-02-05 1964-02-05 Improvements in or relating to semiconductor devices
DE19651268746 DE1268746C2 (en) 1964-02-05 1965-02-03 METHOD OF MANUFACTURING A VARIETY OF PLANAR TRANSISTORS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB493164A GB993388A (en) 1964-02-05 1964-02-05 Improvements in or relating to semiconductor devices

Publications (1)

Publication Number Publication Date
GB993388A true GB993388A (en) 1965-05-26

Family

ID=9786554

Family Applications (1)

Application Number Title Priority Date Filing Date
GB493164A Expired GB993388A (en) 1964-02-05 1964-02-05 Improvements in or relating to semiconductor devices

Country Status (2)

Country Link
DE (1) DE1268746C2 (en)
GB (1) GB993388A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2042586A1 (en) * 1969-08-27 1971-03-11 Hitachi Ltd Field effect semiconductor device
US3772576A (en) * 1967-11-04 1973-11-13 Philips Corp Planar semiconductor device with scribe lines and channel stopper
US4257825A (en) * 1978-08-30 1981-03-24 U.S. Philips Corporation Method of manufacturing semiconductor devices having improvements in device reliability by thermally treating selectively implanted test figures in wafers
DE2949590A1 (en) * 1979-12-10 1981-06-11 Robert Bosch do Brasil, Campinas Integrated circuit with drive and load transistors - incorporates diffused test zones in emitter zones, combined with collector potential contact zone

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL251064A (en) * 1955-11-04

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3772576A (en) * 1967-11-04 1973-11-13 Philips Corp Planar semiconductor device with scribe lines and channel stopper
US3839103A (en) * 1967-11-04 1974-10-01 Philips Corp Semiconductor device and method of manufacturing same
DE2042586A1 (en) * 1969-08-27 1971-03-11 Hitachi Ltd Field effect semiconductor device
US4257825A (en) * 1978-08-30 1981-03-24 U.S. Philips Corporation Method of manufacturing semiconductor devices having improvements in device reliability by thermally treating selectively implanted test figures in wafers
DE2949590A1 (en) * 1979-12-10 1981-06-11 Robert Bosch do Brasil, Campinas Integrated circuit with drive and load transistors - incorporates diffused test zones in emitter zones, combined with collector potential contact zone

Also Published As

Publication number Publication date
DE1268746B (en) 1968-05-22
DE1268746C2 (en) 1976-07-29

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