DE2032838A1 - Verfahren zum Herstellen einer Halb leiterzone durch Diffusion - Google Patents

Verfahren zum Herstellen einer Halb leiterzone durch Diffusion

Info

Publication number
DE2032838A1
DE2032838A1 DE19702032838 DE2032838A DE2032838A1 DE 2032838 A1 DE2032838 A1 DE 2032838A1 DE 19702032838 DE19702032838 DE 19702032838 DE 2032838 A DE2032838 A DE 2032838A DE 2032838 A1 DE2032838 A1 DE 2032838A1
Authority
DE
Germany
Prior art keywords
diffusion
material layer
layer
etching mask
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702032838
Other languages
German (de)
English (en)
Inventor
Kamal 7100 Heilbronn M Merchant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Priority to DE19702032838 priority Critical patent/DE2032838A1/de
Priority to US00157440A priority patent/US3791885A/en
Priority to FR7124166A priority patent/FR2097136B1/fr
Priority to GB3090471A priority patent/GB1324298A/en
Publication of DE2032838A1 publication Critical patent/DE2032838A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
DE19702032838 1970-07-02 1970-07-02 Verfahren zum Herstellen einer Halb leiterzone durch Diffusion Pending DE2032838A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19702032838 DE2032838A1 (de) 1970-07-02 1970-07-02 Verfahren zum Herstellen einer Halb leiterzone durch Diffusion
US00157440A US3791885A (en) 1970-07-02 1971-06-28 Method of manufacturing a semiconductor region
FR7124166A FR2097136B1 (enExample) 1970-07-02 1971-07-01
GB3090471A GB1324298A (en) 1970-07-02 1971-07-01 Method of manufacturing a semi-conductor region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702032838 DE2032838A1 (de) 1970-07-02 1970-07-02 Verfahren zum Herstellen einer Halb leiterzone durch Diffusion

Publications (1)

Publication Number Publication Date
DE2032838A1 true DE2032838A1 (de) 1972-01-13

Family

ID=5775627

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702032838 Pending DE2032838A1 (de) 1970-07-02 1970-07-02 Verfahren zum Herstellen einer Halb leiterzone durch Diffusion

Country Status (4)

Country Link
US (1) US3791885A (enExample)
DE (1) DE2032838A1 (enExample)
FR (1) FR2097136B1 (enExample)
GB (1) GB1324298A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3928081A (en) * 1973-10-26 1975-12-23 Signetics Corp Method for fabricating semiconductor devices using composite mask and ion implantation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514807B2 (de) * 1964-04-15 1971-09-02 Texas Instruments Inc., Dallas. Tex. (V.St.A.) Verfahren zum herstellen einer planaren halbleiteranordnung
US3507716A (en) * 1966-09-02 1970-04-21 Hitachi Ltd Method of manufacturing semiconductor device
US3437533A (en) * 1966-12-13 1969-04-08 Rca Corp Method of fabricating semiconductor devices
DE1764004A1 (de) * 1968-03-20 1971-04-08 Siemens Ag Verfahren zum Herstellen eines Hochfrequenztransistors aus Silicium

Also Published As

Publication number Publication date
GB1324298A (en) 1973-07-25
US3791885A (en) 1974-02-12
FR2097136B1 (enExample) 1974-04-05
FR2097136A1 (enExample) 1972-03-03

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