DE1932716C3 - Circuit arrangement for outputting a number of data signals, in particular formed by switching indicators, from a PCM transmission point of a PCM telecommunications network - Google Patents

Description

management handed over. With the help of this operational

So it is wisely possible to go from pulse frame to pulse frame in each case occurring in directly consecutive time slots of corresponding time channels To be able to record data signals.

With regard to the transmission of data signals

The main patent 1913989 relates to a 30 len from a PCM transmitting station to a PCM process for submitting a number of vg, j ins- receiving point each time there is now the desire to special data formed by switching symbols - the data signals in a different order than the one above To be able to transmit signals from a PCM transmission point of a PCM-viewed. So can according to Telecommunication network in time slots be desirable as a data channel of a CCITT recommendation, in one used time channel from a series of time channels. 35 32-time channel PCM system with 8-bit time slots nals occur with cyclically repeated in pulse frames - when using the 16th time factor within each tender) time fans via a PCM transmission pulse frame as a time slot of a data channel and Route to a PCM receiving point and forwarding. Utilization of the 32nd time factor within each push the relevant data signals over a separate frame as a time slot of a synchronization channel - the Data signal lines of the PCM receiving point. Thereby 40 during the duration of the time slots of the synchronized pedaling the data signals on the transmit side in each case occurring in the channel data signals when submitting select time slots the rest, in particular of the message, the duration of a time slot of the data channel connections used time channels. The highest possible probability of during Pulse frame to pulse frame in each case during the corresponding time slots in other pulse frames Duration of time slots of other time channels occur- 45 to be able to distinguish between transmitted data signals Data signals are in one of the PCMs, namely by z. B. by monitoring the Recording register belonging to the sending station is stored during the time slots of the data channel and from this, for the duration of the respective data signals carried, the end of the next one Time factor of the data channel, agreed number of pulse frames, overstored and forwarded to the PCM receiving center. Can be recognized in 50 frames.

this PCM receiving station are the relevant The invention is based on the object

To show data signals in a corresponding way to the PCM-Receive, like the one shown above recording register belonging to the interception point. Problem can be solved.

chert and from this over the individual time channels to solve the problem outlined above

The invention is based on an individual circuit arrangement Data signal lines output. for the submission of a number of in particular

Thus, by the method considered above, their data formed by switching flags is thus obtained a relatively simple principle used to send data signals from a PCM to a PCM Ferameldenetz from a PCM broadcasting station to a PCM-listening PCM broadcasting station that has a recording register To transmit the receiving point. Thereby one comes with 60, the input side to a data signal Sendein the PCM transmission point is connected to a single set-up device, which is used for data signal acceptance registers from in each case a plurality of data signal elements belonging to each during because other communication links associated with the duration of the time slots of those time channels according to data signals from the PCM transmission point to the PCM emits each other, which can be proven by connections To be able to transmit the receiving point. 65 to which the relevant data signals belong

In one explained in more detail in the main patent, and are on the output side to a PCM transfer Implementation of the procedure described there supply line is connected and to this in each case The circuit arrangement used is used as a transmitting device for the duration of the time slots as a data

The channel used time channel, the previously recorded subjects and which emits data signals in a time slot of the data channel, and the recording of such data- the maximum number of data signals that can be transmitted is signals in a PCM receiving point, which contains an up and on its at certain counter positions actinahmeregister, the input side Transmission line is connected to the PCM fourth counter outputs logic devices and 5 are each connected, which takes the storage part required for the control of the individual partial registers during the duration of the time slots of the data channel and emits this on the output side in one of the control pulses. This measure brings the number of advantages of a relatively simple circuit structure with time channels corresponding to the number provided in addition to the data channel.

According to a further expedient Ausgestalsprechende data signals, according to the patent device of the invention is connected to the respective 1913 989. This circuit arrangement is inventively counting device, the output is characterized according to the fact that the to the signal output according to Output of a counter output data signal transmitting device connected up signal during the duration of a time division of the receiving register from a number of sub-registers is still understood for such a period of time, each of which extends the quotient from the extension, during which the counter concerned normal number of transmits an output signature in a time slot of the data channel. This has the advantage of being able to use data signals and the number of provided data signals that the partial register has a corresponding storage capacity in a relatively simple manner, pulse frame to pulse frame in time slots and that the partial register for a data signal recording with 20 of their time channels occurring data signals in the PCM output by at least one counting device - Broadcasting agency can be included.
Control pulses are applied that occur with such a frequency and phase position that in accordance with the invention, the pulse frame following the counting device is in each case over other time counters belonging to the respective counters when those channels are reached communication links Counter position in which it emits a signal during the data signals in the sub-registers, duration of a time slot of the data channel, and that the sub-registers are transferred to a counter position in which he stores the data stored in them. At the end of this signal output, it outputs a corresponding Sisignal for the duration of a time factor of the signal and then cyclically renews the channel with retrieval control signals and continues the signal output. This measure is suggested, which, as will become apparent further below, channel-time multiples within the respective data channel are distributed to the sub-registers in the desired manner, with the advantage of a relatively low circuit order. see the effort involved. It is enough to have one

The invention is characterized by the advantage of using conventionally constructed counters

that they turn a possibility 35 in a relatively simple way and this by appropriate circuit

offers to modify the measures in a certain fixed order so that he is after a

a PCM transmission point in data signals that are slightly different from its normal counting slip.

the order in which it counts to a PCM receiving diverting counting scheme. Continue to bring this

place to be able to change, so that the measure has the advantage that an otherwise

z. B. during the duration of the time fan a possibly necessary shutdown of the

correct time channel - as the Synchronisierka counter is avoided here.

nals - occurring data signals according to the further expedient refinements and the above Explanations for additional monitoring parts of the invention emerge from the purposes below can be exploited. the description of shown in the drawings

According to an expedient configuration of the first 45 exemplary embodiments.

finding the counter has one of the number F i g. 1 shows a circuit arrangement for the number of partial registers provided through the implementation of the method according to the invention;
Counters, each of which has a counting capacity, the F i g. 2 shows the possible structure of a pre when the sum of the number of in a Pulsrah- shown in Figure 1 circuitry men time cells contained and provided in a 5 Toe "counters.

times of the data channel maximum transferable number Fi g. 3 shows another possible construction

of data signals, and which in its counting capacity is one of the in the circuit arrangement according to FIG.

corresponding cycles in each case at least during the counting devices provided;

one through the maxi in the respective sub-register. Fig. 4 shows yet another possibility of

times einspeicherbare number of data signals gegebe- 55 overall construction of an arrangement of the circuit

A number of time slots, such control signals as shown in FIG. 1, are provided with counting devices;

gives. This is a relatively Fi g in an advantageous manner. 5 is used to clarify the counting device which is shown in a clear circuit structure, each with a large number of FIG

going in the same way structured two circuit processes;

gene achieved. This in turn is advantageous, 60 FIG. 6 serves to illustrate the operation of the if the circuit arrangement in question is shown in the counter shown in FIG. 1,

is to be produced in large numbers. In this case, the circuit arrangement shown in FIG. 1 is then provided with relatively few emittance circuitry including a PCM transmitting station Ss with an associated

groups out. gen data signal output device Ds and one to

According to another useful embodiment 65 of a data signal not shown here

According to the invention, the counting device has a PCM transmitter leading to the counting device and having a counting capacity which is equal to the sum of the path or transmission line L, hereinafter only

Called the number of time PCM transmission lines L contained in a pulse frame. About this

PCM transmission line L will occur from the PCM-PCM transmission line V occurring time slots transmission point 5i and the associated data. In the present case - under the signal output device Ds PCM message signals assuming the presence of eight signal output in each case, time slots comprising elements - the last one

The PCM transmission point Ss contains a PCM transmission 5 considered input of the AND gate GU 3 each transmission line L ', via the PCM message signals z. B. in the 3rd and 5th time element of each time slot an allocated control pulse tb 3, tb S in time slots of communication links. If there are or assigned time channels, the other input of the AND gate G U 3 is transferred from the. The time slots of the total available output ßl of the counter ZE 1 a resulting time channels occur cyclically repeated io speaking control signal, so the control occurs in pulse frames. Optionally, together with the pulse / 63 tbS to the control input £ 5 cause the Aufnahjeweiligen communication links associated reregisters 5Ri 1 and that in entspre communication signals, the PCM transmission site may 5i sponding time compartments each successively the Daauch the respective communication links züge- tensignaleingang Ed of Record register 5Ri 1 output associated data signals. In the present case, 15 data signal elements carried into this recording are assumed to be stored in the message connection registers, namely each corresponding data signals are formed by two times the duration of the 3rd and 5th time element of the je-signal element (bit). According to FIG. 1, the respective time factor. The storage takes place for this purpose two data signal transmission devices, preferably using the edges of the associated changeover switches USa and USb , which ao during the duration of these time elements each have a binary "1" control pulses from their switching arms.

or can enter "0". These binary characters are in addition to the considered counting device ZE1

Speaking signals are provided on the switching contacts of another counter ZE 1 ,

relevant changeover switches USa and USb are constantly on. which belong to the other recording register SRs 2

Which is thus on the switching arms of the switch USa, »5. The counting device ZE 2 is

USb occurring signal elements of the respective data in the same way as the previously considered counter

tens signals throw on separate signal lines direction ZE1 via an AND gate GU 4 and a

5Af α and SMb the inputs of two switches 5a, Sb this downstream OR gate GO 2 to the

supplied, dij operated alternately one after the other. Control input Ei of recording register SR 2 applied.

will. On the other hand, the two 30 are closed. With the help of this counter ZE 2

Switch Sa, Sb connected to one another and then in the receiving register 5Ri 2 in the corresponding

standing in each case designated as data signal input, data signals are stored, which are transmitted by the PCM

Throw inputs Ed of two recording registers 5RiI, 5Ri 2 sending point 5i released. As below

connected. At these inputs Ed, which will throw up even more clearly, throw the two

Receiving registers 5Ril, 5Ri 2 are the receiving registers representing the sub-registers for 35

a data signal recording provided inputs 5RiI, SRs 2 for a data signal recording with from

this register. The counting devices ZE1, ZE 2 each outputted to a data signal

hearing signal elements occur in each case after one- control pulses are applied to those with such

other occur during the duration of a time factor of the frequency and phase position that in successive

that connection uses the time channel, the 40 subsequent pulse frames each over different time

the relevant data signal is associated. Communication links running through channels can be assigned

z. B. the data signals associated with the actuation input pa of the switch Sa in the two sub-registers 5RiI,

For example, throw SRs 2 stored during part of the first half.

Each time slot of the time slots appearing on the PCM transmission line to other inputs of the OR-device L 'considered above, the switch Sa 45 gates GOi and GO 2 throw a transferable control signal to be stored in the shift registers 5RiI, 5Ri 2, and the control input pb of the switch Sb stored data signals serving control pulses can be applied during a part of the second half of each. Such control pulses will be fed to the relevant further input of the mentioned time fan, a corresponding control OR gate GO 1. 5 ° fed from the output of a blocking gate GSl

To the data signal inputs Ed of the recording The corresponding further input of the OR

meregister SRiI, SRs 2 respectively supplied data gates GO 2 throw the corresponding control inputs

store signal elements in these recording registers pulse from the output of an AND gate GU 5

to be able to, these recording registers are still kept. The AND gate GUS is with its one

corresponding control signals or control pulses to 55 input together with the signal input of the

guided. For this purpose throw a control gate GSl to the Aasgang of an AND gate

output Ei of the recording register SR 1 is connected via an OR GU 2 . One input of the AND

GatterGOl from the output of an AND gate GU 3 gates GU2 throw control signals rl6i supplied

Appropriate control signals are supplied. The AND- those within each pulse frame during duration

Gate GU 3 has its one input at the 60 of the 16th time slot (of the data channel). The Output el of a counter ZE 1 connected- other input of AND gate GU 2 throws

sen. This output al of the counting device ZEl control pulses tb supplied. These control pulses ti

are each for a certain number of occur within with the repetition frequency with the one

of each pulse frame on the PCM transmission line, individual ZeiffMchem signal elements occur. Related "

L ' occurring time fan from an output signal. This means that this applies to the conditions assumed above The other input of the AND gate GU 3 throw that eight tax during the duration of a time slot Control pulses supplied, each of which occur at certain pulses tb. Control the control pulses tb Points in time within each time division of the during the duration of the 16th time division of each pulse frame

[9 10

\ metis the AND gate GUS and the blocking gate GS because it can be used, still an AND gate. The previously considered blocking gate GS 1 is on with GU10, which is closed with its output at Rückstellein- \ its blocking input together with a further course of the counter stages forming the counter Zs at the input of the AND gate GU S together. The AND gate 10 indicates GU sides \ output of a further AND gate GU7 reasonable 5 nem output at a certain time within closed. During the half of the respective superframe, this AND gate GU7 emits an output signal 'duration of the 16th time slots within the pulse frame, with the aid of which all counter stages of the counter corresponding control signals are reset to the currently observer Zs . These output signals, inputs of the blocking gate GS1 and the AND output, are used to synchronize the counting gate GU 5 . Exploited on the related- io lers Zs . This will also be discussed further below. The processes will be discussed in greater detail below. The at the output of the AND gate The in F i g. 3 counter shown, the GU7 occurring control signals are also able to fulfill the function of one of the blocking input of a further blocking gate GS 2 and presented in Fig. 1, the one input of another AND gate GU6 15 like the one previously considered Counting device fed to a counter. The blocking gate GS 2 is connected to its signal ler Zs. This counter Zs , however, the input to the output of the shift register SRs 1 control pulses // are connected directly to its counting input. The AND gate GU 6 is with a leads. A shutdown of the counter Zs, as it is connected with the further input to the output of the shift register previously considered embodiment of the counter SRs 2 . On the output side, the blocking ao is done at certain times within the respective gate GS2 and the AND gate GU6 via a gate superframe, is not provided here, the GO 3 to an input of a further AND gate die by the shutdown of the connected to the previously viewer GU 8. This AND gate GU 8 finished embodiment according to FIG. 2, we are fed at a further input control signals kung of the extension of the output signal output / 16 s , which, as already stated above, is here in a different way during each of the counter Zs the duration of the 16th time period is sufficient. As schematically in Fi g. 3 indicated, one of the respective pulse frame occurs. This control AND gate GU 12 with its output at signals are also connected to the blocking input of a white control input of the counter Zs , fed to the lower blocking gate GS 3. The blocking gate The AND gate GU 12 is fed at an input GS3 with its signal input to the PCM over 30 control signals / 16, which are connected during the transmission line V in each case. The output of the duration of the time slots of the data channel occur. This blocking gate GS 3 and the output of the AND gate are based on the GU 8 given above are combined via an OR gate GO 4 - the 16th time slots within each prerequisites. At the output of the OR gate GO 4 there is a 32-time channel pulse frame. The PCM transmission line L is connected to the other input. 35 of the AND gate GU 12, control signals tr4 are added after the previously shown in FIG. 1 shown, which has been explained in each case during the duration of a bed arrangement, should now be correct pulse frame within the respective over the in F i g. 2 to 4 counting device frame shown in more detail occur. This means that the AND gates will be considered. The GUU shown in FIG. 2 is supplied with the same input signals as the counting device contains a counter Zs, whose counting 40 corresponds to the counting or counting device input in the previously considered embodiment. Control pulses from the output of a provided AND gate GU 11 on the closer AND gate GU9 picks up. This AND gate mode of operation of the counter GU9 shown in FIG. 3 is connected with its one input to the alignment, which will be discussed in greater detail below, of a flip-flop FF . At his will.

the other input is taken by the AND gate GU9 the 45 during of the previously considered control pulses // and 3 to be fed to the counter input for the counting devices shown in FIG. Of these control pulses // occurs for each time slot of the circuit arrangement shown, two of the type of devices occurring on the PCM transmission line U are required, FIG. 4 shows a time slot for a pulse. The flip-flop FF has a way, like the two inputs in the circuit arrangement. A counting device ZE1 AND gate GU 11 provided with its output is connected to one input and ZE 2 is formed by a single circuit. This AND gate GI i gives can at its output. This circuit comprises a counter Zs, which during the duration of the time division of the data channel receives counting pulses // at a control input and within a specific pulse frame of each output a 1 during a specific pulse frame forming a superframe a time period within each pulse frame an output signal. Output signal at the output of such a training write The counter Zs has as that of gear signal, the flip-flop FF is zuriickge- the circuit of FIG 3 sets provided counter BR, then causing the operation of the counter Zs a control input, one at the AND-Gattei is interrupted. A Signa-GU12 is only connected to its output on eme feed. This les / 21 at the other input of the flip-hop FF towards 60 AND gate GU12 serves the purpose of bleaching the flip-flop is set again, so that the counter switching provided for in the circuit according to F ι ε 3 Zs can be done. On AND gate GU12. The processes associated therewith are fed to its inputs accordingly signals such as the inputs ter below in connection with FIG. 6 also received the "*" * "·,. ₄ v _{,, C1} . _J. ⁶ S AND gate GV 12. Furthermore, the circuit ge In addition to the elements under consideration, the in Fig. 4 has an AND gate GV 10 assigned, since Fig. 2 shown counting device, which corresponds to the same task as that for each * Both counting tones provided in Fig. 1 each - GatterGUlO in the two previously considered!

individual counter stages of the counter Zs connected .st and that at an output , a 2 in each case, to be determined

appropriately designated switching points of the switching

mkis

rend ^the ^ »^ J ^ g * ^, ^ S the ^» ^ J ^^ Sa ? f ^ ['^ saved.

measured Fig. 1 transferred. * "* J ^ urire

denotes the reference numerals that occur for the exits Signal

are. This is intended to indicate that by

works largely like a conventional binary counter In contrast to a normal binary counter , measures are taken with the counter Zs so that its counting volume is limited to 34. The counter Zs are in the periods corresponding to periods output signals Jai and Yes 2 from, as shown in particular in Fig. 6 will be visible. Thereupon weker below will establish the connection with the in Fig. 6 will be discussed in more detail. G from the diagram according to FII 5? Furthermore ht shows that exists between the Ausgänfenfll and al occurring output signals, a shift corresponding to the duration of half a frame pulse Tp. By outputting output signals offset from one another in this way, the circuits relating to the circuit arrangement according to FIG. 1 belonging slide regulator SRsl and SRsZ data signals are stored. In the following, with reference to FIG. 6 will be discussed in more detail.

The diagram according to FIG. 6 illustrates the time relationships between the occurrence of output signals / el, / a2 at the outputs el and _fl 2 of the circuit arrangement shown in FIG. 4 or at the correspondingly labeled outputs of the counting devices ZE 1 and ZE 2 provided in FIG F i g. 6 it is assumed that the circuit arrangement according to the invention is used in a 32-ZeitkanaI-PCM-System with 8-Bh-Zeiträchern. It is also assumed that the 16th time slot within each pulse frame for the transmission of data signals. Each data signal consists of 2BHs, so that a maximum of 4 data signals can be transmitted within each pulse frame for the duration of the 16 ^ Zettfacher. According to Fig. 6 are generated with the aid of the output signal IaI d, e which occurs during the duration of the pulse beam RS RS, R 6 and

in Fig. 6th

30th

35 previously acquired Shift register still>

this ^ "^ J ^
from the output of the duration of the 16th Z control signal

During the year
however, are measures

an otherwise ^^^^^ Τ Einspe.cherung, the W ^ ¹¹¹ J _{that in the}

^ f ^ l ^ S dawn signals in the

During the £ _{ah R} 8 a M this counter with

£ S _with ßeendi- Β ^ * 8 | ^ j that nem

submission of a ^ J '^ ™ _from | _bt ^B _Be . an output signal ια2 on the AW «* _ag rfmm

pulled; on ^ ™, J ₁₅ ¹ ξ. ⁵ _P U4 indicates this that d, e ^ Fifr 4 ^ ag _ ^ ^

night -without ^ outside a 17. Paying ^ rgerulvrt w Creation gives the ^ J ^^^

gangssjgnal IaI from considered normal board members

Fig. 'KargestenIten ff ^ reference to the m ^r ' f *? F ^ T noticed that di «

tang been explained ^ «» gjg ^ ,, ratio. ***? ^ J »*** ji ^ S 3 also shown 1bei ^Anw ^ *« ^ ^d " VL circuit arrangement th ^ ™" ^ ¹ ^ ™, ϊΓrSei ^^ licher zi

on top

_{the waiter}

w _the ir Bc

note, JJ
Counting devices

shows ^

was hoped, the withdrawal is no longer of data signal on these shift registers examined more closely. As already indicated above, the

signal from the ^ gf ^ ™ «rtes data signal from ^^ S ^^ Sf SS" sound signal

*O

If DiSui-rimpulses occur each Sd of the duration of the 16th time path of each pulse frame. As indicated in Fig. 1, either control impulses tx or control impulses ty can occur during the duration of the 16th multiple times of each pulse frame. The control pulses tx have twice the pulse frequency as the control pulses ty. If the output of the AND gate GU1, the control pulses tx occur for the duration of the 16th time period of each pulse frame, the result is that the data signals stored in the shift registers SRsI and SRs2 are stored in the following order-

First data signal from the shift register SRs 2 - first data signal from the shift register SRi 1 - second data signal from the shift register SRsI - second data signal from the shift register Stepping in contrast to the just be At the outset, we * the eme Betaebswe.se "n with regard to the evaluation of the data signals transmitted in the time slots of the data channel are of particular advantage, namely, during the duration of the It: division of each Pukrahmens in the shift register SRsI two binaries. "0" is saved at I for the duration te ; 32. ZeU-fold each pulse frame also uses the bit combination "00", so it is seen when driving in the circuit arrangement according to FIG

AND gate GVl mriJ ^^ JJJjgy ^ '5 possible, the m the shift registers SRs 2, SRs 1 during the duration of the time divider * 31, * 32 in the pulse frame R1 and during the duration of the time, fächerftl5, * 16 m the pulse frame Ä «To output stored data signals in the following sequence: data signal-fc31; Data signal- * 15; Data signal-fc 32; Data signal for 16.

For this purpose 2 sheets of drawings

Claims (10)

Patent claims: 1.Circuit arrangement for outputting a number of data signals, in particular formed by switching indicators, from a PCM transmission point, which contains a recording register which is connected on the input side to a data signal transmission device which outputs data signal elements belonging to data signals one after the other during the duration of the time slots of those time channels which can be occupied by connections to which the data signals in question are associated, and which is connected on the output side to a PCM transmission line and to which it outputs the previously recorded data signals for the duration of the time slots of a time channel used as a data channel, and the recording of such data signals in a PCM receiving point which contains a recording register which is connected on the input side to the PCM transmission line and which records data signals for the duration of the time slots of the data channel and which on the output side in one of the numbers the corresponding number of intermediate memories provided in addition to the data channels present in addition to the data channels are connected, which each record corresponding data signals, according to Patent 1913 989, characterized in that the recording register connected to the data signal transmission device (USa, USb) consists of a number of sub-registers (SRs 1, SRs 2) , each of which has a storage capacity corresponding to the quotient of the number of data signals that can be transmitted in a time slot of the data channel and the number of sub-registers (Sflsl, SRs 2) provided , so that the sub-registers (SRsI, SRs2) Un receive a data signal with at least a counting device (ZEi, ZE2) issued control pulses are applied, which occur with such a frequency and phase position that in successive pulse frames each message connections running over other time channels associated data signals are stored in the sub-registers (SRsI, SRs 2) , and that the sub-registers (SRsI , SRs2) for extracting the data signals stored in them for the duration of a time factor of the data channel with extracting control signals (tx; ty), which are distributed to the sub-registers (SÄsl, SRs 2) in the desired order within the respective data channel time slot. 2. Circuit arrangement according to claim 1, characterized in that the counting device (ZEl, ZE 2) has a number of counters (Zi) corresponding to the number of partial registers provided (SR ν 1, SRs 2), each of which has a counting capacity equal to that Sum of the number of time slots contained in a pulse frame and the maximum number of data signals that can be transmitted in a time slot of the data channel, and the corresponding cycles in its counting capacity at least during one given by the maximum number of data signals that can be stored in the respective sub-register (SRsI, SRs2) Number of time slots emits control signals. 3. Circuit arrangement according to claim 1, characterized in that the counting device (ZEl, ZE2) has a counter (Zs) with a counting capacity equal to the sum of the number of time subjects contained in a pulse frame and the maximum in a time slot of the data channel The number of data signals which can be transmitted is and to whose counter outputs, activated at certain counter positions, logic devices (GU 13) are connected, which emit the storage control pulses required to control the individual sub-registers. 4. Circuit arrangement according to one of claims i to 3, characterized in that in the counter (Zi) belonging to the respective counting device (ZEl, ZE 2 ) the output signal output after outputting an output signal for the duration of a time multiple of the data channel for such a period of time is extended during which the counter concerned normally emits an output signal. 5. Circuit arrangement according to claim 4, characterized in that, to extend the delivery of a counter output signal, the further counting of the respective counter (Zs) is stopped by reversing a flip-flop (FF) at a point in time at which the counter (Zs ) emits an output signal in the one time slot (k 16) of the data channel, and that the flip-flop (FF) is reset again at a point in time (/ 21) within the relevant pulse frame at which the counter (Zs) switches on after it has been stopped Output signal has emitted in a duration corresponding to the duration of the normal delivery of an output signal. 6. Circuit arrangement according to one of claims 1 to 3, characterized in that the respective counter (Zs) belonging to the counting device (ZEl, ZE2 ) upon reaching the counter position in which it outputs a signal for the duration of a time division (k 16) of the Outputs data channel, is transferred to a counter position in which, following this signal output, it outputs a corresponding signal in the relevant other counter position and then repeatedly continues the signal output zn klisch. 7. Circuit arrangement according to claim 6, characterized in that the respective counter (Zs) can be changed in its counter position via a logic gate (GU 12) which is activated at its one input when a certain counter position (ir 4) of the counter (Zs) is reached and which is acted upon at its other input with control pulses (t 16 s) occurring during the duration of the time slots (k 16) of the data channel. 8. Circuit arrangement according to one of claims 2 to 7, characterized in that the counters (Zs) provided in each case are synchronized, preferably in each case by a signal element occurring in the last time element of the last time factor of the last pulse frame of a superframe comprising a number of pulse frames. 9. Circuit arrangement according to one of the claims! to 8, characterized in that the storage of the partial registers (SRsI, SRs2) the data signals contained in each case by activating the sub-registers (SRsI, SRsI) and enabling? its outputs can be changed with the help of control pulses (tr, ty) occurring at different frequencies 10. A circuit arrangement according to claim 9, characterized in that to switch the storage of data signals from the sub-registers (SRsI, SRs 2) in each desired term recording register uses a shift register that has one of the maximum number in a time slot of the data channel transmittable data signal elements has a corresponding number of register stages. 5 This recording register records the number of Time fans occurring within the respective pulse frame data signal elements recorded. According to one examined in more detail in the main patent In the sequence of the _{example for the inclusion of control 10} , in a first pulse frame R 1 of a pulse-serving input (Es) of a partial eight pulse frame A1 to RS comprehensive control pulses (SRs2) are each over one mens during the duration of the first four time slots Al to k4 occurring data signals or data signal elements recorded in the recording register registers AND circuit (GU S) are supplied and at the output of the same sub-register (SRs 2)
Shl (Eq / 6) for di Fig AND circuit (GU 6) for the delivery of data i ₅ and during the tens signals. is activated while at the same time
corresponding inputs and outputs of the other sub-registers (SRsI) during the occurrence
the relevant control pulses via locking gates
(GS 1, GS 2) are blocked. in the concerned Pulse frame occurring time slot Jk 16 of the time channel used as the date channel is transmitted via the PCM transmission line. During the following pulse frame R 2 , during the time slots A: 5 to k 8 occurring data signals or data signal elements are recorded by the recording register and during the duration of the next time slots of the data channel again via the PCM over-