DE1932716B2 - Circuit arrangement for outputting a number of data signals, in particular formed by switching indicators, from a PCM transmission point of a PCM telecommunications network - Google Patents

Description

5 6

channel used the previously recorded subjects and that in a time slot of the data channel Sends data signals, and recording such data is the maximum number of data signals that can be transmitted signals in a PCM receiving station that has an up and an actinahmeregister at certain counter positions contains logic devices on the input side to the PCM fourth counter outputs Transmission line is connected and 5 are each connected, which are used for controlling the during the duration of the time slots of the data channel individual sub-registers required storage and emit it on the output side in one of the control pulses. This measure brings the Number of the advantage of a relatively simple circuit structure that is present in addition to the data channel Appropriate number of time channels are provided.

Intermediate storage is connected, each ent- io According to a further expedient Ausgestalsprechende Record data signals, according to the patent device of the invention is used in the case of the respective 1913 989. This circuit arrangement is a counter belonging to the inven- tion according to the output characterized in that the signal output after output of a counter output data signal transmitting device connected signal for the duration of a time factor of the receiving register from a number of sub-registers still understands the data channel for such a period of time, each of which extends one of the quotient from the extension, while the relevant counter normal number an outputs an output signal in a time slot of the data channel in a transfer manner. This brings the ble data signals and the number of advantages provided that in a relatively simple manner of Partial register has corresponding storage capacity, pulse frame to pulse frame each in time slots the sub-registers for a data signal recording with 20 of their time channels occurring data signals in the can be received by at least one counting device issued PCM transmission point. Control pulses are applied with such According to a further useful Ausgestal frequency and phase position occur that in turn the invention becomes the counting device other pulse frames each via other time-related respective counters when that one is reached Channels running communication links trains 25 counter setting in which he received a signal during the subordinate data signals are fed into the sub-registers be chert, and that the sub-registers are transferred to a counter position in which it is stored in the respective data stored in them, a corresponding signal output to this signal output emits a time multiple of the signal for the duration and then cyclically repeats the channel with withdrawal control signals 30 fetches the signal output continues. This measure be suggested, which brings within the respective data, as will be seen below, channel time times on the sub-registers in the desired order the advantage of a relatively low circuit technology be distributed. see the effort involved. It is enough to have one The invention is characterized by the advantage of being able to measure meters that are constructed in the usual way they turn around a possibility in a relatively simple way and offer this through appropriate circuitry, to modify the measures in a certain fixed order so that he is after a data signals fed to a PCM transmission point differ slightly from its normal counting scheme Order in which it counts to a PCM receiving diverting counting scheme. Continue to bring this place to be able to change, so that measure has the advantage that an otherwise signed. B. during the duration of the time fan a possibly necessary shutdown of the correct time channel - as the Synchronisierka counter is avoided here.

nals - occurring data signals according to the further expedient refinements and the above Explanations for additional monitoring parts of the invention emerge from the purposes below can be exploited. the description of shown in the drawings

According to an expedient configuration of the first 45 exemplary embodiments.

finding the counter has one of the number F i g. 1 shows a circuit arrangement for the provision Partial register corresponding number to the implementation of the method according to the invention; Counters, each of which has a counting capacity, the F i g. 2 shows the possible structure of a equal to the sum of the number of in a pulse frame in FIG. 1 shown circuit arrangement vorgemen contained time subjects and the counting devices seen in a time 50;

times of the data channel maximum transferable number F i g. 3 shows another possible construction

of data signals, and which in its counting capacity is one of the in the circuit arrangement according to FIG. 1

corresponding cycles in each case at least during the counting devices provided;

one through the maxi in the respective sub-register. Fig. 4 shows yet another possibility of

times the number of data signals that can be stored.

A number of time slots, such control signals as shown in FIG. 1, are provided with counting devices;

gives. In this way, a relatively F i g. 5 serves to illustrate the in

Clear circuit structure, each with a wide range of F i g. 5 counting device shown running down

going in the same way structured two circuit processes;

gene achieved. This in turn is advantageous, 60 FIG. 6 is used to illustrate the operation of the

if the circuit arrangement in question is relatively in FIG. 1 shown counting device,

is to be produced in large numbers. In this case, the circuit arrangement shown in FIG. 1 comes

one then with relatively few unit circuits includes a PCM transmission point Sä with an associated

groups out. gen data signal output device Ds and one to

According to another useful embodiment 65 of a data signal not shown here

According to the invention, the counting device has a counting device leading PCM transmission

ler with a counting capacity that is equal to the sum of the route or transmission line L, hereinafter only

Called the number of time PCM transmission lines L contained in a pulse frame. About these

I 932 716

7 8

PCM transmission line L will occur from the PCM-PCM transmission line L ' occurring time slots transmitting point Ss and the data associated with this. In the present case are - below the signal output means Ds PCM message signals acceptance of the presence of eight Signalabgegeben, elements comprising time slots - the last PCM transmission site Ss includes a PCM-over- 5 considered input of the AND gate GU 3 each tragungsleitung L ' , via the PCM message signals, for example in the 3rd and 5th time element of each time slot, a control pulse tb 3, tb 5 allocated in time slots of communication links is supplied. If there are any or assigned time channels, the other input of the AND gate GU 3 is transferred from the. The time slots of the total available output α 1 of the counting device ZE1 a resulting time channels occur cyclically repeated io speaking control signal, so the control occurs in pulse frames. If necessary, together with the pulses tb 3, tb 5 to the control input Es of the respective message connections associated meregister SRs 1 and cause the time slots in the corresponding message signals may the PCM transmitting station Ss to pull one after the other according to the respective message connections Ed des Recording register SRs 1 output associated data signals. In the present case, 15 data signal elements routed in this recording are assumed to be stored in the message connection registers, namely each corresponding data signals are formed by two times the duration of the 3rd and 5th time element of the je-signal element (bit). According to FIG. 1, the respective time factor. The storage takes place for this purpose two data signal transmission devices, preferably using the edges of the associated changeover switches USa and USb , the 20 during the duration of these time elements occurring from their switching arms a binary "1" control pulses.

or can enter "0". These binary characters are in addition to the considered counter ZEl

Speaking signals are constantly applied to the switching contacts of the respective changeover switch USa and USb provided yet another counter ZE 2. which belongs to the other recording register SRs 2 which is thus on the switching arms of the changeover switch USa, 25. The counting device ZE 2 is in ent- USb occurring signal elements of the respective corresponding manner as the previously considered counting signal are via separate signal lines direction ZE1 via an AND gate GU 4 and a 5Ma or SMb the inputs of two switches Sa, Sb this The downstream OR gate GO 2 is fed to the control input Es of the recording register SR 2 which is actuated alternately one after the other. On the other hand, the two 30 are closed. Using this counter ZE 2 who switches Sa, Sb connected to each other and to demand the stored in the receiving register SRs 2 in a corresponding standing respectively referred to as data signal input, data signals of two of the PCM inputs .ED pickup register SrSi, SRs 2 transmitting station Ss to be submitted. As attached below. At these inputs Ed, which will become more apparent, the input registers 5i-51, SRs2 are the input registers SRsI, SRs 2 provided for data signal recording for data signal recording from this register. The hearing signal elements outputted to one data signal in each case by the counting devices ZE1, ZE 2 are applied one after the other 40 other pulse frames each time the relevant data signal is associated with a different time. Communication links running through channels can be added. B. the actuation input pa of the switch Sa associated data signals in the two sub- registers SRsI, for example during part of the first half SRs 2 are stored.

each time factor of the on the PCM transmission line- To further inputs of the OR-

device L ' occurring time slots a the switch Sa 45 gates GO 1 and GO 2 are supplied to make transferable control signals to be stored in the shift registers SRs 1, SRs 2 , and the control input pb of the switch Sb serving control pulses serving the control input pb of the switch Sb during a part the second half each laid. Such control pulses will be fed to the relevant further input of the mentioned time fan, a corresponding control OR gate GOl. 50 supplied from the output of a blocking gate GSl.

In order to be able to store the data gates GO 2 respectively fed to the data signal inputs Ed of the recording The corresponding further input of the OR-meregisterSi? Il, SRs 2 , the corresponding control signal elements are stored in these recording registers from the output of an AND gate GU 5 these recording registers are still kept. The AND gate GU 5 is fed with its corresponding control signals or control pulses to 55 input together with the signal input of the. For this purpose, a control gate GS1 is connected to the output of an AND gate gang Es of the recording register SRsI via an OR GU 2 . Control signals 16s are fed to one input of the AND gate GOl from the output of an AND gate GU 3 gate G £ 72, and corresponding control signals are fed here. The AND, which occurs within each pulse frame during the duration of gate GU3 , has its one input at the 60 of the 16th time slot (of the data channel). The output al of a counting device ZE1 is connected to the other input of the AND gate GU 2. This output al of the counting device ZEL is supplied with control pulses tb . These control pulses tb are each for a certain number of within occur with the repetition frequency with which in each of the pulse frames on the PCM transmission line individual time fans signal elements occur / related L ' occurring time fans from an output signal. 65 to the ratios assumed above, this means that the other input of the AND gate GU 3 is supplied with eight control pulses during the duration of a time division, each of which occurs at specific pulses tb . The control pulses tb control points in time within each time division on the during the duration of the 16th time division of each pulse frame

9 10

mens the AND gate GUS and the blocking gate GS because it can be used, still an AND gate. The previously considered blocking gate GS 1 is open with GU 10, which is closed with its output at reset in its blocking input together with another gear of the counter stages forming the counter Zs at the input of the AND gate GU5. The AND gate GU 10 indicates that the output of a further AND gate GU1 is included in an output at a specific point in time. During the half of the respective superframe, this AND gate GU 7 emits an output signal duration of the 16th time slots within the pulse frame, with the aid of which all counter stages of the counter corresponding control signals are reset to the currently viewed Zs . These output signals, inputs of the blocking gate GS 1 and the AND output, are used to synchronize the counting gate GS / 5. Exploited on the related- io lers Zs . This will also be discussed further below. The processes will be discussed in greater detail below. The at the output of the AND gate The in F i g. 3 counting device shown, the

GUl occurring control signals are also able to fulfill the function of one of the blocking inputs shown in Fig. 1 of a further blocking gate GS 2 and counting devices, which contains an input of a further AND gate GU 6 15 like the previously considered counter. The blocking gate GS 2 is connected to its signal ler Zs. This counter Zs , however, the input to the output of the shift register SRs 1 control pulses tf are connected directly to its counting input. The AND gate GU6 is with a leads. A shutdown of the counter Zs, as it is connected with the further input to the output of the shift register previously considered embodiment of the counter SRs 2 . On the output side, the blocking takes place at certain times within the respective gate GS1 and the AND gate GU 6 via a gate superframe, is not provided here, the GO 3 to an input of a further AND gate die due to the shutdown des connected to the previous viewer GE / 8. This AND gate G U8 ended embodiment according to FIG. 2, we are fed at a further input control signals kung of the extension of the output signal output t16s , which, as already explained above, each from the counter Zs is here in a different way during the duration of the 16th time period is enough. As schematically in Fi g. 3 indicated, one of the respective pulse frame occurs. This control AND gate GU 12 with its output at signals are also connected to the blocking input of a white control input of the counter Zs , fed to the lower blocking gate GS 3. The blocking gate The AND gate GU 12 is fed at an input GS 3 with its signal input to the PCM transmission 30 control signals il6, which are each connected during the transmission line Z /. The output of the duration of the time slots of the data channel occur. This blocking gate GS 3 and the output of the AND gate are based on the GU 8 given above are combined via an OR gate GO 4 - the sixteenth time slots within each are summarized. At the output of the OR gate GO 4 there is a 32-time channel pulse frame. The PCM transmission line L is connected to the other input. 35 of the AND gate GU12 , control signals fr4 are

After ^{1 the} scarf shown in FIG. 1, which was explained during the duration of an operation, should now be correct pulse frames within the respective over the in FIG. 2 to 4 counting device frame shown in more detail occur. This means that the AND gates will be considered. The in F i g. The Gt / 12 shown in FIG. 2 are supplied with the same input signals as the counting device contains a counter Zs, the counting 40 of which is the same as the counting or counting input in the previously considered embodiment. Control pulses from the output of a provided AND gate GU 11. On the closer AND gate GU 9 picks up. This AND gate mode of operation of the counter GU9 shown in FIG. 3 is connected with its one input to the alignment, which will be discussed in greater detail below, through a flip-flop FF . At his will.

the other input is taken by the AND gate G U9 45 While of the previously considered control pulses tf and 3 to be fed to the counter input in FIG. 2 for the counting devices shown in FIG. 1 on. Of these control pulses tf , two of the type of devices occurring on the PCM transmission line Z / occur per time slot of the circuit arrangement shown, FIG. Time fans an impulse. The flip-flop FF has a way, like the two inputs in the circuit arrangement. At one input there is a counting device ZE1 AND gate GU 11 provided with its output and ZE2 is formed by a single circuit. This AND gate G11 gives can at its output. This circuit comprises a counter Zs, which receives counting pulses tf at a control input for the duration of the time division of the data channel and within a certain pulse frame of each output a I during a certain pulse frame forming a superframe a time period within each pulse frame Output signal. On issuing such an output signal emits. The counter Zs has as that of gear signal, the flip-flop FF is zurückge- the circuit of FIG. 3 provided counter Zs • sets, whereby then the operation of the counter Zs a control input to the AND gate (is interrupted. Its output is only connected to a supply of a signal GU 12. This Iesi21 at the other input of the flip-flop FF 60 AND gate GU 12 serves the same purpose as when the flip-flop is set again, so that the , the g in the circuit of F i. 3 provided for indexing of the counter Zs done. on AND gate GU 12, its inputs are therefore hereby associated operations will then continue supplied to corresponding signals as the inputs ter below in connection with FIG. 6 that will be included in the circuit according to FIG. 3. ·, .... 6 ₅ AND gate GU 12. Furthermore, the circuit is

In addition to the elements under consideration, an AND gate GU 10 assigned in FIG. 4, the counter shown in FIG. 2, which has the same task for each of the two corresponding ones in FIG. 1 provided counting devices per gate GU 10 in the two previously considered

11 12

Circuits according to FIGS. 2 and 3. It should be time slots corresponding to duration. As in connection, therefore, it is unnecessary to go into this in more detail. In the lower part with F i g. 5 explained above, enters an output signal, however, different to the previously-considered embodiments, la 1 corresponding to half the duration of a Pulsrahist here a further AND gate GU 13 upstream mens Tp seen Ia2 after the occurrence of an output signal that turns with its inputs to outputs 5 on. When the signal Ia 1 occurs, the alternating counter stages of the counter Zs are connected rend the duration of the time slots k 1, k 2 in the pulse and that at an output a2 in each case at certain frames / ?! occurring data signals in the points in time emits an output signal. Shift register SRs 1 according to FIG. 1 stored.

To clarify the functioning of the in As in F i g. 6 indicated by arrows, the circuit shown in FIG. 4 is considered in more detail with the diagram previously set in the shift registers SRs2 and SRsI in FIG. 5. In this slide stored data signals during the duration of the program denote the time 16 times plotted on the left side 16 of the pulse frame k R 1 ausgespeigenen letter /, e, d, c, b, al, and α 2 chert which corresponds and the PCM transmission line L speaking designated circuit points of the switching dimension F i g. 1 transferred. With the occurrence of the next device according to FIG. 4. The output of the counting signal Ia 2 is denoted for the duration of the lers Zs and the output of the AND gate GU 13 with time compartments k 19 and k 20 in the pulse frame R 1 on the reference numerals for the outputs entering data signals into the shift register SRs 2 in the circuit arrangement according to FIG. 1 contained stored. When the next signal occurs, the counters ZE 1 and ZE2 used are finally IaI for the duration of the. This is intended to indicate that by means of time slots k 3 and k 4 in the pulse frame R 2, the circuit according to FIG. 4 are stored in circuit points of the circuit arrangement which speak to the emerging data signals in the shift register SRs 1. During the duration of the 16th time multiplication according to FIG. 1 the functions of the 16 provided there in the pulse frame R 2 are fulfilled by the relevant counting devices ZE1 and ZE 2 , data signals from the shift registers can be output again. It should be evident from FIG. 5 that it stores 25 and that the counter Zs is a counter that transmits the transmission line L via the PCM shown in FIG. The above works largely like a conventional binary counter. In the intended processes repeat themselves in an analogous difference to a normal binary counter, however, measures are taken during the following pulse frames R3, R 4, the counter Zs , so that R 5, R 6 and R 7, as in particular those in FIG. 6 its counting volume is limited to 34. The number of arrows shown can be seen
During the duration of the eighth pulse frame R 8 periods, Zs emits output signals Yes 1 and Yes 2 in the time span tz. However, measures are effective which, in particular, from FIG. 6 an otherwise occurring change in the order of the will become visible. The connection with the storage of the data signals in the slide in the diagram shown in FIG. 6 is prevented in more detail below, registers SRs2, SRsI , and is included in the. From the diagram according to the sequence explained above, data signals in FIG. 5 also show that they are still stored between the shift registers. For outputs a 1 and a 2 occurring output this purpose is the counter Zs according to FIG. 4 signals a shift corresponding to the duration of the output of the AND gate GU 12 during which half a pulse frame Tp is present. By 40 duration of the 16th time multiple in the pulse frame R 8, an output control signal that is offset from one another in this way is supplied, in response to which this counter with signals are terminated at different times, i.e. with the termination of the circuit arrangement according to FIG 1 against the output of a signal IaI at output a1, listening shift register SRs 1 and SRs 2 data - outputs an output signal Ia 2 at output a 2 . Beacons stored. The 45 related to the in FIG. In the following, this means that the processes shown in FIG. 4 shown counting on F i g. 6 will be discussed in more detail, direction - without being stopped - in the

The diagram according to FIG. 6 illustrates the 17th counter position being transferred. In this counting-time relationship between the occurrence, the counter Zs according to FIG. 4 an output from output signals IaI, Ia2 at the outputs oil 5 ° output signal Ia2 . Following this, the normal counting operation considered above and 2 of the circuit arrangement shown in FIG. 4 is continued,
The above is the data signal recording in the case of the in FIG. 1 provided counting devices F i g. 1 shown circuit arrangement under Be ZE1 and ZE2. According to FIG. 6, it is assumed that with reference to the counting device shown in FIG. 4, the circuit arrangement according to the invention has been explained in a device. It should be noted, however, that the 32-time channel PCM system with 8-bit time slots is shown in particular from FIG. 6 is used. It is also assumed that the 16th time is also used when using the illustrated in Fig. 2 and 3 within each pulse frame for transmission th counters in the circuit arrangement of data signals. Each data according to FIG. 1 can be achieved. There is only to signal from 2 bits, so that during the duration of the 60 note that the output signal output of the 16th time times within each pulse frame maximum counting devices ZE 1 and ZE 2, as shown above, 4 data signals can be transmitted. According to FIG. 6 is shown, corresponding to half the duration of a pulse beam with the aid of the offset during the duration of the pulse frame Tp. Takes place in contrast to the occurring in mens R 8 output Ia2 the counter shown in Figure 4 Fig. At Anwährend the duration of the time bins F7 and k 18 Open 65 turn of counters in FIG. 2 and 3 passing data signals in the shift register SRs 2, the extension of Output signal output from that of FIG. 1 is stored. The signal Ia2 has the respective counter Zs during the duration of the 4th pulse, so one of the duration of two successive frames of the 8 pulse frames each

frame. This is explained in the main patent and therefore does not need to be considered further here.

After the storage of data signals in the shift registers SRs 1 and SRs 2 had previously been considered, the storage of data signals in these shift registers will now be examined in more detail. As already indicated above, the storage of data signals from the shift registers SRsI and SRs2 takes place with the aid of control pulses which are emitted from the output of the AND gate GU 7 belonging to the circuit arrangement according to FIG. These control pulses occur for the duration of the 16th time of each pulse frame. As in Fig. 1 indicated, either control pulses tx or control pulses ty can occur during the duration of the 16th time factor of each pulse frame. The control pulses tx have twice the pulse frequency as the control pulses ty. If the control pulses tx occur at the output of the AND gate GUl during the 16th time of each pulse frame, the result is that the data signals stored in the shift registers SRs 1 and SRs 2 are output in the following order:

First data signal from shift register SRs 2 ■ - first data signal from shift register SRs 1 - second data signal from shift register SRs 2 - second data signal from shift register SRsI. If, in contrast to the case just considered, the control pulses ty occur at the output of the AND gate GUl, the data signals stored in the relevant shift registers are output in the following order: first data signal from shift register SRs 2 - second data signal from shift register SRs 2 - ■ first data signal from the shift register SRs 1 - second data signal from the shift register SRI.

In this way it is possible to output the respectively recorded data signals in one of two possible sequences. As stated at the outset, the one mode of operation with regard to the evaluation of the data signals transmitted in each case in the time slots of the data channel can be of particular advantage. If two binary characters "0" are stored in the shift register SRsI for the duration of the 16th time slot of each pulse frame and the bit combination "00" is also used for the duration of the 32nd time slot of each pulse frame, this is the case when the in the Circuit arrangement according to FIG. 1 provided AND gate GU1 with the help of the control pulses ix possible, which in the shift registers SRs 2, SRsI during the duration of the time slots k 31, k 32 in the pulse frame R 7 and for the duration of the time slots k 15, k 16 in the pulse frame R 8 output stored data signals in the following order: data signal- &31; Data signal &15; Data signal &32; Data signal-M6.

For this purpose 2 sheets of drawings

Claims (10)

Patent claims: 1.Circuit arrangement for outputting a number of data signals, in particular formed by switching indicators, from a PCM transmission point, which contains a recording register which is connected on the input side to a data signal transmission device which outputs data signal elements belonging to data signals one after the other during the duration of the time slots of those time channels which can be occupied by connections to which the data signals in question are associated, and which is connected on the output side to a PCM transmission line and to which it outputs the previously recorded data signals for the duration of the time slots of a time channel used as a data channel, and the recording of such data signals in a PCM receiving point which contains a recording register which is connected on the input side to the PCM transmission line and in each case receives data signals during the duration of the time slots of the data channel and the output side with one of the number of next to the data channel existing time channels corresponding number of provided buffers is connected, which each record corresponding data signals, according to patent 1913 989, characterized in that the recording register connected to the data signal transmission device (USa, USb) consists of a number of sub-registers (SRs 1, SRs 2) , each of which has a storage capacity corresponding to the quotient of the number of data signals that can be transmitted in a time slot of the data channel and the number of sub-registers (SRsI, SRs2) provided that the sub-registers (SRsI, SRs 2) for data signal recording with at least one Counting device (ZEl, ZE 2) issued control pulses are applied, which occur with such a frequency and phase position that in successive pulse frames each message connections running over other time channels associated data signals are stored in the subregisters (SRsI, SRs 2) , and that the subregisters (SRsI , SRs 2) to extract the data signals stored in them for the duration of a time slot of the data channel with extract control signals (tx; ty), which are distributed to the sub-registers (SRsI, SRs 2) in the desired order within the respective data channel time slot. 2. Circuit arrangement according to claim 1, characterized in that the counting device (ZEl, ZE 2) has a number of counters (Zs) corresponding to the number of partial registers (SRs 1, SRs 2) , each of which has a counting capacity equal to the sum the number of time slots contained in a pulse frame and the maximum number of data signals that can be transmitted in a time slot of the data channel, and the corresponding cycles in its counting capacity at least during one of the maximum number of data signals that can be stored in the respective sub-register (SRs 1, SRs 2) given number of time slots emits control signals. 3. Circuit arrangement according to claim 1, characterized in that the counting device (ZEl, ZE 2) has a counter (Zs) with a counting capacity equal to the sum of the number of time subjects contained in a pulse frame and the maximum transmittable in a time slot of the data channel The number of data signals is and to whose counter outputs activated at certain counter positions logic devices (GU 13) are connected, which emit the storage control pulses required for the control of the individual sub-registers. 4. Circuit arrangement according to one of claims 1 to 3, characterized in that in the counter (Zs) belonging to the respective counting device (ZE 1, ZE 2) the output signal output after outputting an output signal for the duration of a time multiple of the data channel for such Period of time is extended during which the counter concerned normally emits an output signal. 5. Circuit arrangement according to claim 4, characterized in that, to extend the delivery of a counter output signal, the further counting of the respective counter (Zi) is stopped by reversing a flip-flop (FF), namely at a point in time at which the counter (Zs ) emits an output signal in the one time slot (k 16) of the data channel, and that the flip-flop (FF) is reset at a point in time (t2l) within the relevant pulse frame at which the counter (Zs) has an output signal after it has been stopped has delivered in a duration corresponding to the duration of the normal delivery of an output signal. 6. Circuit arrangement according to one of claims 1 to 3, characterized in that the respective counter (Zs) belonging to the counting device (ZE 1, ZE 2) when that counter position is reached in which it outputs a signal for the duration of a time division (k 16 ) of the data channel, is transferred to a counter position in which it outputs a corresponding signal in the relevant other counter position following this signal output and then continues the signal output cyclically and repeatedly. 7. Circuit arrangement according to claim 6, characterized in that the respective counter (Zs) can be changed in its counter position via a logic gate (G U 12), which at its one input when a certain counter position (ir 4) of the counter (Zs) is reached is activated and which is acted upon at its other input with control pulses (t 16 s) occurring during the duration of the time fan (k 16) of the data channel. 8. Circuit arrangement according to one of claims 2 to 7, characterized in that the counters (Zs) provided in each case are synchronized, preferably in each case by a signal element occurring in the last time element of the last time factor of the last pulse frame of a superframe comprising a number of pulse frames. 9. Circuit arrangement according to one of claims 1 to 8, characterized in that the storage in the sub-registers (SRs 1, 3 4 SRsZ) in each case contained data signals by term recording register a shift register is used, control of the sub-registers (SRsI, SRs 2) and one of the number of maximum in a time slot release of their outputs with the help of data signal elements of different frequencies that can be transmitted with the data channel Number of register levels, sen (tx; ty) can be changed. 5 This recording register records the 10. Circuit arrangement according to claim 9, during a certain, fixed number of characterized in that, for switching, time fans within the respective pulse frame of the storage of data signals from the occurring data signal elements are added. Ge sub-registers (SRs 1, SRs 2) in each desired order of the order considered in more detail in the main patent, the example for receiving control, are in a first pulse frame R 1 of an input (Es) serving for pulses of one sub-eight Pulse frames Rl to RS comprehensive Überrahregisters (SRs 2) control pulses are each supplied via a mens during the duration of the first four time slots AND circuit (GU 5) and data signals or data output of the same sub-register (SRs 2) occurring at kl to k4 signal elements are added to the recording register: AND circuit (GU 6) for the delivery of data 15 and is activated during the duration of the relevant tens signals, while at the same time pulse frame occurring time slot k 16 of the data corresponding inputs and outputs of the remaining channel used Transmission line transmitted via the PCM-Übergen subregisters (SRsI) during the occurrence. During the following of the relevant control pulses via blocking gates, pulse frames R 2 are blocked during time slots k 5 (GS 1, GS 2). 20 to k 8 occurring data signals or data signal elements taken from the recording register and for the duration of the next following time subjects of the data channel is released again via the PCM transmission line. With the help of this operational So it is possible to go from pulse frame to pulse frame in immediately successive steps To be able to record data signals occurring in time fans of corresponding time channels. With regard to the transmission of data signals The main patent 1913 989 relates to a 30 len from a PCM transmitting station to a PCM process for submitting a number of ins- receiving points, there is now a desire to "special data formed by switching symbols - the data signals in a different order than the one above To be able to transmit signals from a PCM transmission point of a PCM-viewed. So can according to Telecommunication network in time slots be desirable as a data channel of a CCITT recommendation, in one used time channel from a series of time channels. 35 32-time channel PCM system with 8-bit time slots nals occur with cyclically repeated in pulse frames - when using the 16th time factor within each trending time slots via a PCM transmission pulse frame as a time slot of a data channel and route to a PCM receiving point and forwarding use of the 32nd time slot within each push the relevant data signals over a separate frame as a time slot of a synchronization channel - the Data signal lines of the PCM receiving point. Thereby ^ o during the duration of the time slots of the synchronized pedaling the data signals on the transmit side in each case occurring in the channel data signals when submitting select time slots the rest, in particular of the message, the duration of a time slot of the data channel connections used time channels. The highest possible probability of during Pulse frame to pulse frame in each case during the corresponding time slots in other pulse frames Duration of time slots of other time channels occur- 45 to be able to distinguish between transmitted data signals Data signals are in one of the PCMs, namely by z. B. by monitoring the Recording register belonging to the sending station is stored during the time slots of the data channel and from this, during the duration of the data signals carried, the end of the one following each one Time factor of the data channel, agreed number of pulse frames, overstored and sent to the PCM receiving center. To be able to recognize in 5 ° frame. this PCM receiving station are the relevant The invention is based on the object To show data signals in a corresponding way to the PCM-Receive, like the one shown above recording register belonging to the interception point. Problem can be solved. chert and from this over the individual time channels to solve the problem outlined above individually associated buffer to the incoming 55, the invention is based on a circuit arrangement individual data signal lines output. for the submission of a number of in particular With the method considered above, their data generated by switching indicators is So a relatively simple principle is used to send data signals from a to a PCM telecommunications network from a PCM broadcasting station to a PCM-listening PCM broadcasting station that has a recording register Timpfangsstelle to transmit. Thereby one comes with 60, the input side to a data signal Sendein the PCM transmission point is connected to a single set-up device, which is used for data signal acceptance registers from in each case to a multiplicity of data signal elements belonging to each each during / because other communication links associated with the duration of the time slots of those time channels according to data signals from the PCM transmission point to the PCM emits each other, which can be proven by connections To be able to transmit the receiving point. 65 to which the relevant data signals belong In the case of one explained in more detail in the main patent, and the output side to a PCM transmission to carry out the procedure described there supply line is connected and to this respectively The circuit arrangement used is used as a transmitting device for the duration of the time slots as a data