DE1932718C3 - Circuit arrangement for the transmission of data signals associated with communication links connected through a PCM exchange via the PCM exchange - Google Patents

Description

The main patent 19 13 990 relates to a method for the transmission of communication links maintained via a PCM exchange of a PCM telecommunications network, in particular data signals relating to switching indicators, via the PCM exchange. The data signals received by the PCM exchange and the data signals to be emitted by it are transmitted in time slots of a time slot that is used as a common data channel and is combined with the time slots of time slots for communication links in pulse frames, with a criterion for the assignment between the time slots in the time slots of a pulse frame existing communication links and the data signals that belong to these in detail and are transmitted in the common file. The data signals recorded by the PCM switching center in the time slots of the common data channel used on the receiving side of the PCM exchange are, after being temporarily stored in a recording register, individually stored in the receiving side of the associated message connection and transmitted ^{via the PCM exchange c} ; the data signals transmitted in this way, after being temporarily stored in an output register, are output from the PCM exchange during the time slot of the time slot assigned to the relevant message connection of the common data channel used on the transmission side of the PCM exchange.

With the help of the method considered above, it is achieved that the reception and delivery of a A large number of data signals, in particular formed by switching indicators, in or from a PCM exchange of a PCM telecommunications network on a relative basis can be carried out in a simple manner without the quality of the respective communication link being reduced, as is the case with known ones Orders or procedures is the case. It is also achieved that in the PCM exchange the over data signals associated with these respectively running communication links during the duration the time slots of the time channels associated with the relevant communication links are available. As a result, the respective communication link relevant measures such. B. triggering a connection, already be carried out with their signaling.

In connection with the method considered above, it is proposed in the main patent specification, the above-mentioned recording register and the Above also mentioned delivery registers with output signals from counters assigned to them in each case apply, the counter capacity of which is equal to the

Sum of the number of time slots belonging to a pulse frame and the number in one Time slot of the data channel is each transmittable data signals. These counters each give in their Counting capacity corresponding cycles from an output signal, in each case during the duration of one of the Number of corresponding number of data signals that can be transmitted in a time slot of the respective data channel from time subjects p

In connection with the above-mentioned counters it has now been shown that their output signal output must be lengthened at certain times so that data signals are recorded in each case can belong to the connections routed from pulse frame to pulse frame via other time channels are. To solve this problem it is proposed in the main patent specification to continue counting the counter after the occurrence of data signals in time slots that immediately precede the time slot of the data channel, for the duration of the relevant time slot of the data channel immediately following: n the time fold of the data channel in the same Pu.srahmen to prevent occurring data signals leading time slots. This is done with the help of two AND gates and one upstream of the counter input Flip-flop comprehensive circuit. With the help of this circuit, the counter is set according to the above indicated conditions shut down.

The invention now has for its object to indicate a way in which the above-indicated so to be carried out extension of dispensing an "output signal from a counter, with the output signals of a receiving register and an output register is applied, can be made in a simpler manner than in the main patent is proposed

In order to achieve the object indicated above, the invention is based on a circuit arrangement For transmission from via a PCM exchange of a PCM reporting network, in particular Data signal relating to the switching indicator via the PCM exchange, the ones received by the PCM exchange and those received by it data signals to be output in time slots of one with the time slots of for communication links in Considered time channels combined in pulse frames, serving as a common data channel Time channel are transmitted and with a criterion for the assignment between the time channels in such a way of a pulse frame existing communication links and the associated with these in detail, im common data channel transmitted data signals the time slots of the time slots of the common data channel within a multiple pulse frame comprehensive (Form superframes, in addition to which the common file channel of data signals recorded by the PCM exchange after being temporarily stored in a recording registers from this individually in each case in the receiving-side time slot of the relevant associated message connection and transmitted via the PCM switching center and in this way transmitted data signals after intermediate storage « in an output register from this in each case during the time slot of the time slot assigned to the relevant message connection on the transmission side of the PCM exchange used common data channel issued by the PCM exchange are, for which purpose the receiving register and the output register are supplied with output signals from counters assigned to them, the counting capacity of which is equal to the sum of the number of each a pulse frame belonging time fan and the number of each in a time slot of the data channel transmittable data signals and the cycles corresponding in their counting capacity during the Duration of one of the number of data signals that can be transmitted in a time slot of the respective data channel emit an output signal according to patent 19 13 990. According to the invention, this circuit arrangement is characterized in that the respective counter after the End counter position in which it outputs an output signal for the duration of a time division of the data channel releases, without stopping it is transferred to a counter position in which it follows the straight ensuing signal output emits a corresponding output signal in this other counter position and in the Following this, the output signal output continues cyclically and repeatedly.

Compared to the measure of the extension of the output signal applied according to the main patent delivery from the respective counters at the specified times mentioned brings the according to the invention Measure with the advantage of a relatively low circuit complexity. It takes namely to be taken care only that the respective counter after reaching its final counter position during a certain pulse frame of one number each! is transferred from successive pulse frames comprehensive acquisitions to another counter position.

According to an expedient embodiment of the invention, it is used to transfer the respective counter in said one counter position an output signal emitted by a logic gate, the je »: ils occurs when the logic gate is on his one input is activated by the counter in the final counter position and at his other input a control signal from this input for the duration of the time slots of the data channel picks up respectively supplied control signals

This advantageously results in a particularly low circuit complexity for the extension of the output signal output from the respective counter. It is also advantageous that a Ordinary counter can be used, with no special between individual counter stages Schal.'Tiaßungen are to be taken to extend the relevant output signal output.

An exemplary embodiment of the invention is explained in more detail below with the aid of drawings

F i g. 1 shows the possible structure of a data signal recording device of a PCM exchange;

F i g. FIG. 2 illustrates the temporal relationships of the in FIG. 1 data signal recording device occurring processes

The in F i g. The data signal recording device De shown in FIG. 1 is shown here ν , · as far as is necessary for understanding the present invention. One possible structure of the entire data signal recording device is explained in detail in the main patent. The data signal recording shown in Fig. 1

Meeinrichtung De is connected with an input e to a PCM transmission link or PCM line PCM . This PCM line or PCM line - hereinafter referred to as PCM line for short - leads to the input of a PCM switching network not shown here. Message signals associated with communication links are transmitted via the PCM line L , specifically in time slots of time channels assigned to the communication links in question. As stated in the main patent, these time channels have time slots nested in one another and recurring cyclically in pulse frames. In addition to the message signals, data signals are transmitted via the PCM line L for the duration of the time slots of a time channel of the available time channels used as a data channel, which are in particular formed by switching indicators and which are associated with the connections that are made via the others

£ .cilKiiuaiG * tiiauivii.

One input of an AND gate GU 1 is connected to the input of the Dalensignalaufnahmeeinrichtung De. Control signals 1 16e are fed to the other input of AND gate CU 1. These control signals 1 16e contact respectively the duration of the time bins of the data channel used on the PCM line L on. Based on the relationships described in the main patent, it is also assumed here that a PCM system with 32 time channels is present and that the time channel in the 16th position in the loan sequence is used as the data channel. Accordingly, an activation or control signal / 16e should appear within each pulse frame at the last input of the AND gate CU ^{1 I considered during the occurrence of the 16th time.} The data signals appearing on the PCM line L are thus picked up correctly by the data signal recording device De and fed from the output of the AND gate GU 1 via an OR gate GO to the input of a shift register SRe used for data signal storage. This shift register SRe has a storage capacity which corresponds to the maximum number of data signal elements occurring in a time slot of the data channel. Assuming that in the assumed 32-time channel PCM system, the individual time slots each comprise 8 bits, i.e. a maximum of 8 bits can be transmitted in the time slots of the data channel, the shift register SRe has a storage capacity of 8 BiL

The already mentioned OR gate CO is connected with a further input to the output of an AND gate GU2 . This AND gate GU2 is connected with its one input , m to the output of a counter Ze. Control signals ie 'are fed to a further input of this AND gate GU 2. Two control signals occur per time slot of these control signals te'. It should thus be taken into account here that the data signals to be passed on from the output of the data signal recording device De in individual time slots each comprise two bits. With regard to the conditions assumed above (8-bit shift register SRe), this means that data signals relating to four communication links are stored in the shift register SRe.

The counter Ze has a counting capacity which is equal to the sum of the number of time slots belonging to a respective pulse frame and the number of data signals that can be transmitted in a time slot of the data channel.

d. H. assuming the assumption of a 32-channel PCM system with 8-bit time slots and the transmission of four data signals in one time slot of the data channel, this means that the counter Ze

^r , has a counting capacity of 36. In the cycle of this counting capacity, the counter Ze emits output signals at its output connected to one input of the AND gate GU2. The duration of the output signals corresponds to a duration of four

ίο time fans (corresponding to the number of data signals stored in each case in the shift register SRe). To advance the counter Ze , its control or counter input is used to control signals Ik, of which one signal occurs for each time slot.

The counter Ze also has a further control input to which an AND gate GU3 is connected with its output. This AND gate GU3 is activated at its one input for the duration of a ": hritimmten pill frame" of each pulse frame forming a superframe. For this purpose, the relevant one input of the AND gate GU3 ^ '-cuersignals tr5 are fed. Control signals 1 16e are fed to gate GU3. These control signals r 16e occur in each case

2Ϊ during the duration of the time slots of the data channel. Consequently, an output signal occurs at the output of the AND gate GU3 for the duration of the time factor of the data channel in • ien'ijenigp ': pulse frame of the pulse frame forming a superframe, in which one

jo corresponding control of the counter ZE is to be carried out to extend the output signal output. This is referred to below in connection with FIG. 2 will be discussed in more detail.

The counter Ze is still an AND gate GU4

r>, which is connected with its output to the reset inputs of all counter stages of the counter Ze . A control signal fr32r8 is fed to one input of the AND gate Gi / 4. This control signal occurs whenever the counter Ze emits a signal indicating the last time slot (line slot 32) of the pulse frame. A control signal tbS is fed to the other input of the AND gate GU 4. This control signal occurs during the duration of the eighth signal element within each time slot. An output signal occurs at the output of the AND gate GU4 when the eighth signal element of the designated last (32nd) time slot occurs within the last pulse frame of the superframes comprising a total of 8 pulse frames

so on. This output signal is fed to the reset inputs of the counter stages of the counter Ze, it thus synchronizes the counter Ze. The counter Ze is thus brought into a certain position, namely into its starting position, at a certain point in time within each superframe, provided that it is not already in this position, which is the case with error-free operation.

According to FIG. 2 it is assumed that there is a 32-time channel system in which the 16th time channel is used as a data channel. It is also assumed that eight signal elements are transmitted in each of the individual time slots and that the data signals transmitted in the time slots of the data channel are each formed by 2 bits. This means that four data signals relating to connections can be transmitted in each time slot of the data channel. The data signals occurring in the time slot k 16 of the data channel in the pulse frame R 1 are, as shown in FIG. 2 illustrates

forwarded during the duration of the time slots ArI to k 4 of the following pulse frame R 2 together with the message signals occurring in the relevant time slots. For this purpose, the counter Ze considered above emits an output signal for the duration of the time slots k \ to k 4 . in this Ausgani "^ ignal out occur at the output of the AND gate GU? corresponding output signals, the data signals contained in the shift register SRe are stores that help. the data signals in the time slot Ar 16 occurring of the pulse frame Rl are as F i g 2 shows that during the duration of the time slots λ 5 to Ar 8 of the next following pulse frame R 3 together with the message signals occurring in the relevant time slots. The data signals occurring in time slot Ar 16 of the pulse frame R 3 are, as can be seen, during the duration of the Time compartments Ar 9 to Ar 12 of the following pulse frame R 4 together with the time compartments in question forwarding message signals. The data signals occurring in the time slot Ar 16 of the pulse frame RA are forwarded during the duration of the time slots Ar 13 to k 15 of the subsequent pulse frame R 5 together with the message signals occurring in the relevant time slots. In contrast to the conditions considered above, there are only three data signals relating to connections. The data signals occurring in the time slot Ar 16 of the data channel in the pulse frame R 5 are forwarded for the duration of the time slots Ar 17 to Ar 20 of the same pulse frame R 5 together with the message signals occurring in the relevant time slots. The data signals occurring in the time fans Ar 16 of the following pulse frames Λ 6, R 7 and R 8 are each included in the time fans Ar 21 to * 24 or k 25 to k 28 or * 29 to Ar 32 of the same pulse frame forwarded to the message signals occurring in the relevant time slots.

To the distribution of the in the cell A: 16 of the respective pulse frame, explained in principle above the Counter Ze, as stated above, a counting volume that is equal to the number of occurrences in a pulse frame The number of time slots plus the number of time slots in which the Ar 16 occurring data signals can be forwarded. As already stated above, the counter Ze considering the assumed circumstances, a counting volume of 36; he is designed so that he emits an output signal for the duration of four time slots and normally, ie in the event that it is not controlled at other inputs, does not emit an output signal for the duration of a pulse frame (32 time slots). In other words, this means that the interval between the occurrence of an output signal at the output of the counter Ze and the repeated occurrence of a corresponding output signal is the number of time slots of a pulse frame plus the number of time slots in which data signals occur in a time slot of the data channel can be distributed. This distance is shown in FIG. 2 denoted by Iz.

As stated above, in the pulse frame R 5 according to FIG. 2 a division of data signals twice. For this purpose, the counter Ze is activated separately via the AND gate GlJ J when the time slot Ar 16 occurs in the pulse frame R 5. In response to this additional activation, the counter Zc is transferred to such a counter position in which it continues its output signal output, specifically for a period which corresponds to the normal output signal output duration. The counter Ze, which is not stopped or shut down during this process, emits a corresponding output signal in connection with the time slot Ar 16 in the pulse frame R 5 for the duration of the subsequent time slots Ar 17 to Ar 20. After this extension of the output signal output from the counter Ze, as shown in FIG. 2, normal operation continues again. The counter Ze then cyclically outputs output signals repeatedly until the AND gate GU3 is activated again and outputs an output signal at its output. This is the case for the duration of the time slot Ar 16 in the pulse frame R 5 of the following superframe, which also includes eight pulse frames R 1 to R 8.

Finally, it should be noted that the measures considered above with regard to the control of the counter Ze provided in the data signal recording device De can also be applied in the same way to a counter as is provided on the output side of a PCM switching center in order to be there in individual time slots of message connections assigned time channels to record occurring data signals and to output them combined in each case in a time slot of a data channel. The associated processes of the data signal output device to be provided accordingly, as explained in detail in the main patent, therefore need not be discussed in more detail here.

1 sheet of drawings

Claims (2)

Patent claims: 1.Circuit arrangement for the transmission of data signals assigned via a PCM switching center of a PCM telecommunications network, in particular data signals relating to switching indicators, via the PCM switching center, with the data signals received by the PCM switching center and those being withdrawn from it. Transmitting data signals in time slots of one with the time slots of for communication links in ZeilkanäJen to be considered combined in pulse frames, serving as a common data channel Time channel are transmitted and with a criterion for the assignment between the in the Time channels of a pulse frame and the communication links to these in detail associated Daie.isignalen transmitted in the common data channel, the timings of the time slots of the common data channel within a Form multiple pulse frames comprehensive upper frame, furthermore in the time subjects of the the receiving end of the PCM exchange used a common data channel from the PCM exchange recorded data signals after being temporarily stored in a recording register from this individually in each case in the time slot of the relevant associated message connection stored on the receiving side and are transmitted via the PCM exchange and the data signals transmitted in this way after being temporarily stored in an output register from this in each case during the time slot of the relevant message connection associated time slot of the common data channel used on the transmission side of the PCM exchange from the PCM exchange, including the receiving register and the delivery register with output signals from each of them assigned- * ο th counters whose counting capacity is equal to the sum of the number of π each time fan belonging to a pulse frame and the number of times in a time slot des Data channel is each transmittable data signals and the cycles corresponding in their counting capacity for the duration of one of the number emit an output signal in a time slot corresponding to the number of time slots that can be transmitted to data signals in a time slot of the respective data channel. % according to patent 19 13990, characterized in that the respective counter (Ze), after reaching the end counter position in which it issues an output signal for the duration of a time factor of the data channel, is transferred to a counter position without stopping, in which it is then switched to the signal output currently taking place outputs a corresponding output signal in this other counter position and then continues the output signal output in a cyclical manner. 2. Circuit arrangement according to claim 1, characterized in that for transferring the respective counter (Ze) 'm said one counter position is an output signal emitted by a logic gate (GU3) which occurs when the logic gate (GLJ3) at its one Input a control signal (I f6ej from this input receives control signals supplied during the duration of the time slots of the data channel and receives a trigger signal at its other input, which occurs during the duration of that pulse frame in which the counter (Ze) in question emits an output signal for the duration of the time slot of the data channel