DE1809115A1 - Verfahren zur Herstellung von mehrere Schichten umfassenden Leitungsverbindungen fuer Halbleiteranordnungen - Google Patents

Verfahren zur Herstellung von mehrere Schichten umfassenden Leitungsverbindungen fuer Halbleiteranordnungen

Info

Publication number
DE1809115A1
DE1809115A1 DE19681809115 DE1809115A DE1809115A1 DE 1809115 A1 DE1809115 A1 DE 1809115A1 DE 19681809115 DE19681809115 DE 19681809115 DE 1809115 A DE1809115 A DE 1809115A DE 1809115 A1 DE1809115 A1 DE 1809115A1
Authority
DE
Germany
Prior art keywords
layer
metallic
insulating layer
conductor
metallic conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19681809115
Other languages
German (de)
English (en)
Inventor
Cunningham James Alan
Clark Robert Scotland
Lathrop Jay Wallace
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE1809115A1 publication Critical patent/DE1809115A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19681809115 1968-02-14 1968-11-15 Verfahren zur Herstellung von mehrere Schichten umfassenden Leitungsverbindungen fuer Halbleiteranordnungen Pending DE1809115A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70550268A 1968-02-14 1968-02-14
FR176185 1968-12-02

Publications (1)

Publication Number Publication Date
DE1809115A1 true DE1809115A1 (de) 1969-08-21

Family

ID=26182347

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681809115 Pending DE1809115A1 (de) 1968-02-14 1968-11-15 Verfahren zur Herstellung von mehrere Schichten umfassenden Leitungsverbindungen fuer Halbleiteranordnungen

Country Status (5)

Country Link
US (1) US3597834A (enExample)
DE (1) DE1809115A1 (enExample)
FR (1) FR1600505A (enExample)
GB (1) GB1240189A (enExample)
NL (1) NL6816415A (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3838442A (en) * 1970-04-15 1974-09-24 Ibm Semiconductor structure having metallization inlaid in insulating layers and method for making same
FR2134172B1 (enExample) * 1971-04-23 1977-03-18 Radiotechnique Compelec
US3832769A (en) * 1971-05-26 1974-09-03 Minnesota Mining & Mfg Circuitry and method
JPS4835778A (enExample) * 1971-09-09 1973-05-26
US3961414A (en) * 1972-06-09 1976-06-08 International Business Machines Corporation Semiconductor structure having metallization inlaid in insulating layers and method for making same
US4001870A (en) * 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
FR2206583B1 (enExample) * 1972-11-13 1976-10-29 Radiotechnique Compelec
US4041896A (en) * 1975-05-12 1977-08-16 Ncr Corporation Microelectronic circuit coating system
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
JPS5370688A (en) * 1976-12-06 1978-06-23 Toshiba Corp Production of semoconductor device
US4182781A (en) * 1977-09-21 1980-01-08 Texas Instruments Incorporated Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating
US4259367A (en) * 1979-07-30 1981-03-31 International Business Machines Corporation Fine line repair technique
DE3006117C2 (de) * 1980-02-19 1981-11-26 Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern Verfahren zum Herstellen von Leiterplatten mit mindestens zwei Leiterzugebenen
US4383270A (en) * 1980-07-10 1983-05-10 Rca Corporation Structure for mounting a semiconductor chip to a metal core substrate
US4528582A (en) * 1983-09-21 1985-07-09 General Electric Company Interconnection structure for polycrystalline silicon resistor and methods of making same
US4789760A (en) * 1985-04-30 1988-12-06 Advanced Micro Devices, Inc. Via in a planarized dielectric and process for producing same
WO1987000686A1 (fr) * 1985-07-16 1987-01-29 Nippon Telegraph And Telephone Corporation Bornes de connection entre des substrats et procede de production
US4638400A (en) * 1985-10-24 1987-01-20 General Electric Company Refractory metal capacitor structures, particularly for analog integrated circuit devices
JP2502511B2 (ja) * 1986-02-06 1996-05-29 日立マクセル株式会社 半導体装置の製造方法
JPH0763064B2 (ja) * 1986-03-31 1995-07-05 株式会社日立製作所 Ｉｃ素子における配線接続方法
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
US5075259A (en) * 1989-08-22 1991-12-24 Motorola, Inc. Method for forming semiconductor contacts by electroless plating
US5260234A (en) * 1990-12-20 1993-11-09 Vlsi Technology, Inc. Method for bonding a lead to a die pad using an electroless plating solution
JP3051569B2 (ja) * 1992-05-29 2000-06-12 新光電気工業株式会社 多層リードフレーム
US5371328A (en) * 1993-08-20 1994-12-06 International Business Machines Corporation Component rework
US5609704A (en) * 1993-09-21 1997-03-11 Matsushita Electric Industrial Co., Ltd. Method for fabricating an electronic part by intaglio printing
EP0685113B1 (en) * 1993-12-20 1999-11-03 General Electric Company Method of repairing a conductive line of a thin film imager or display device and structure produced thereby
JP3420706B2 (ja) * 1998-09-22 2003-06-30 株式会社東芝 半導体装置、半導体装置の製造方法、回路基板、回路基板の製造方法
US6911230B2 (en) * 2001-12-14 2005-06-28 Shipley Company, L.L.C. Plating method
US7192890B2 (en) * 2003-10-29 2007-03-20 Intel Corporation Depositing an oxide

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3169892A (en) * 1959-04-08 1965-02-16 Jerome H Lemelson Method of making a multi-layer electrical circuit
US2890395A (en) * 1957-10-31 1959-06-09 Jay W Lathrop Semiconductor construction
LU38614A1 (enExample) * 1959-05-06
US3287612A (en) * 1963-12-17 1966-11-22 Bell Telephone Labor Inc Semiconductor contacts and protective coatings for planar devices
US3264402A (en) * 1962-09-24 1966-08-02 North American Aviation Inc Multilayer printed-wiring boards
US3319317A (en) * 1963-12-23 1967-05-16 Ibm Method of making a multilayered laminated circuit board
US3312871A (en) * 1964-12-23 1967-04-04 Ibm Interconnection arrangement for integrated circuits
US3383568A (en) * 1965-02-04 1968-05-14 Texas Instruments Inc Semiconductor device utilizing glass and oxides as an insulator for hermetically sealing the junctions
US3419765A (en) * 1965-10-01 1968-12-31 Texas Instruments Inc Ohmic contact to semiconductor devices
US3495324A (en) * 1967-11-13 1970-02-17 Sperry Rand Corp Ohmic contact for planar devices

Also Published As

Publication number Publication date
GB1240189A (en) 1971-07-21
FR1600505A (enExample) 1970-07-27
NL6816415A (enExample) 1969-08-18
US3597834A (en) 1971-08-10

Similar Documents

Publication Publication Date Title
DE1809115A1 (de) Verfahren zur Herstellung von mehrere Schichten umfassenden Leitungsverbindungen fuer Halbleiteranordnungen
DE3339957C2 (enExample)
DE2319883C3 (de) Verfahren zum Herstellen von Leitermustern auf einer Halbleiteranordnung
DE2554691C2 (de) Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung
DE1903961B2 (de) Integrierte Halbleiterschaltung und Verfahren zu ihrer Herstellung
DE4446881A1 (de) Durchgangsloch und Herstellungsverfahren eines Durchgangslochs
DE1952578A1 (de) Verfahren zur Herstellung metallischer Kontakte auf Halbleiterkoerpern
DE2722557A1 (de) Verfahren zum aufbringen von metallisierungsmustern auf einem halbleitersubstrat
EP0005185A1 (de) Verfahren zum gleichzeitigen Herstellen von Schottky-Sperrschichtdioden und ohmschen Kontakten nach dotierten Halbleiterzonen
DE2033532C3 (de) Halbleiteranordnung mit einer Passivierungsschicht aus Siliziumdioxid
DE69114346T2 (de) Verfahren zum Herstellen von mehrlagigen koplanaren Leitungs-/Isolator-Schichten unter Verwendung von lichtempfindlichem Polyimid.
DE1943519A1 (de) Halbleiterbauelement
DE2123595A1 (de) Halbleiteranordnung
DE1766297A1 (de) Verfahren zum Anpassen einer integrierten Schaltung an ein als Traeger dienendes Substrat
DE2230171A1 (de) Verfahren zum herstellen von streifenleitern fuer halbleiterbauteile
DE1589076C3 (de) Verfahren zum Herstellen von Halbleiteranordnungen mit tragfähigen elektrischen Leitern
DE1764758A1 (de) Verfahren zum Bilden von Anschlussleitungen an einen Koerper aus Halbleitermaterial
DE1812130B2 (de) Verfahren zum herstellen einer halbleiter- oder dickfilmanordnung
DE19501693C2 (de) Verfahren zum Herstellen von elektronischen Bauelementen und mit diesem Verfahren hergestelltes elektronisches Bauelement
DE3112215A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE69215956T2 (de) Verfahren zum Herstellen eines Kontakts auf einem Halbleiterbauelement
DE68907237T2 (de) Verfahren für die Herstellung von metallisierten Löchern in einem Substrat durch eine Metallablagerung im Vakuum und auf diese Weise hergestelltes Produkt.
DE1564528A1 (de) Verfahren zum Herstellen eines elektrisch leitenden Kanals in einem kristallinen Halbleiterkoerper
DE1564136C3 (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE1937508B2 (de) Verfahren zur herstellung eines mit elektrischen leitungsbahnen und/oder elektrischen durchkontaktierungen versehenen isolierstofftraegers