DE1293217B - Circuit arrangement for further processing and comparison, in particular for forming the difference between the forward and backward counting pulse sequences supplied by a digital pulse generator - Google Patents

Description

The invention relates to a circuit arrangement for further processing and for comparison, in particular to form the difference from a digital pulse generator supplied up and down counting pulse sequences.

In numerical control of work machines such as B. the of machine tools, digital-incremental position or angle measuring systems are often used used. Here, a pulse emitted by this measuring system corresponds to a certain, z. B. Distance increment covered by a tool slide.

The location measuring method is then based on counting continuously from a certain starting position.

The disadvantage of this measuring method is that once it has occurred Counting error all other measurement data falsified.

Such a digital incremental measuring system can, for. B. consist of a line grid attached to the tool slide, which is queried by two fixed scanning heads offset by 901 el. From the two mutually offset pulse trains occurring in the scanning bodies, it is then determined with the aid of logic circuits in which direction the machine is running - forwards or backwards - and, depending on the case, forward or backward counting pulses are sent to a downstream up and down counter.

The reading of this counter is then a measure of the actual coordinate value of the moving tool slide. Due to mechanical vibrations, which are often unavoidable when clamping and processing the workpiece, it can happen that the machine vibrates and that path pulses are then emitted almost simultaneously in both directions at a very high frequency, e.g. B. with a frequency of 100 kI-1z.

Various methods and arrangements are now known to form the difference between two pulse trains.

With one of these arrangements, each incoming pulse becomes the one to be compared Pulse series are initially stored in a first memory assigned to each pulse series and then retrieved at a certain point in time and transferred to a difference counter In this case, the pulses are transferred indirectly to the difference counter two more memories, the contents of which are in sync with one another in the cycle of a sampling frequency be compared that a positive or negative counting pulse only then on the downstream differential counter is given if only in one of the two memories a pulse is present. The two uncorrelated pulse series are therefore initially Ordered in time so that a minimum interval between the pulses is guaranteed and no Pulse in the difference counter can be lost.

Furthermore, a method for the ongoing static determination of the difference between the counter readings of two electronic counters is already known, in which the counters each consist of a multi-link chain of binary levels. For comparison, the control states are simultaneously queried in pairs at the outputs of the binary stages of the two counters, which are directed in the same way, in a manner known per se and are compared with one another. From the control states of each pair of binary stages, both the difference and the transfer according to amount and sign are then separately obtained as a control signal sequence by comparison switching means.

Furthermore, there is also a method for forming the difference between Pulse trains known using up counters, in which the lower digits, where the difference between the two values can be more than one, in each case a decade counter, and the higher digits where the difference between both values is not more than one, registered in each of a multivibrator whereupon an oscillator is connected to both decade counters and these can be incremented synchronously until the decade counter that has the lower of the registered both absolute values, zero and the other decade counter the one between shows the difference between the two values.

This latter method has the disadvantage that the determination the pulse difference takes a relatively long time, whereas the Known methods explained above are disadvantageous in that they have a require great effort.

You therefore had to use normal up-down counters Accept that some pulses will be lost in an incremental measuring process.

It should also be noted in this context that it is already in itself is known to build multi-stage counters with runtime memories and also to use runtime memory as actual value memory.

The object of the present invention is to prevent these counting errors by using a simple comparison element which does not even need to be designed for the maximum pulse frequencies that occur. This object is achieved with a device of the type mentioned at the beginning, in which the forward and backward counting pulses each reach an intermediate counter and are here comparable with one another, in that a one-bit adder-subtracter is provided for comparison as an actual value memory serving circulating memory, and that with each circulation of the memory only the bit of the highest position of each counter can be transferred to the one-bit adder-subtracter and then deleted in the intermediate counter.

This also applies during the transfer of the pulses to the comparison element no pulses can be lost, are advantageously the intermediate counter there is also a pre-store connected upstream, which stores the pulses generated during the transmission to save. Outside the transmission time, the forward and reverse pulses can then be used be pushed through the pre-store at the clock frequency of the circulating store.

A simple two or two counters is particularly suitable as an intermediate counter three-stage binary counter; however, other counters, e.g. B. decimal counter, be used.

The invention will be explained in more detail using a drawing.

Fig. 1 shows a basic circuit diagram of the system, Fig. 2 shows the structure of the preliminary and intermediate storage.

The pulse trains supplied by a pulse generator are fed to a logic evaluation circuit 2 (a so-called quarter-division logic). This then emits pulse trains at its outputs Y and R which correspond to the paths covered in the forward or reverse direction. From the logic evaluation circuit 2 on, the pulses of the forward and backward movement are processed further in separate channels 3 and 4.

Both channels 3 and 4 have the same structure. The pulses supplied by the logic evaluation circuit 2 first arrive in each of the preliminary memories 5 and 6, which are each designed for two bits. Here the pulses are pushed through in the cycle of a downstream circulating memory, which will be explained later, and arrive in three-stage binary counters 7 and 8, respectively.

The status of these counters 7 and 8 is queried periodically from time to time. During this interrogation time, a lock 13 ensures that no more pulses can reach the binary counters 7 and 8 from the preliminary memories 5 and 6.

Only the highest digit of the counter readings is processed further and, in each case, fed to an adder-subtracter 11 with the corresponding digit of the other binary counter. These highest places are then deleted.

The adder-subtracter 11 is in the circulation path of an actual value memory 12 designed as a magnetostrictive circulating memory, which z. B. rotates at a frequency of 5 kH. In the one-bit adder-subtracter 11 , the variable b taken over from the binary counter 7 is added to a digital variable a already present in the circulating memory 12 at the relevant point, and the variable c taken over from the binary counter 8 is subtracted. If there is a positive or negative transfer d, it is processed like the variables b or c. Since only one bit is processed per cycle, the input signal and the transmission can never occur at the same time. In contrast, the sizes b and c can be processed at the same time. The use of a one-bit adder-subtractor in connection with a circular memory means that relatively little effort is required.

Since the significance of the individual digits is characterized by the chronological sequence in a circular storage system, all processes such as addition, synchronization, queries and deletion must of course be synchronized. For this purpose, a built up of logic elements control unit 9, which receives its times from a clock 10 , the z. B. works with a clock frequency of 300 kHz.

The processing of the pulses described above ensures that forward and backward counting pulses occurring almost simultaneously cannot be lost, but are stored until they can be processed. If the machine approaches the desired end position at creep speed, the pulse frequency is very low; the count accumulated in intermediate counters 7 and 8 can be reduced. The then still arriving pulses are immediately passed to the one-bit adder-subtracter 11 , since the first digit of the binary counter is now queried.

F i g. 2 shows one of the channels, e.g. B. the channel 3. This consists essentially of the two-bit pre-memory 5 and the three-stage binary counter 7.

A pulse occurring at the output V of the logic evaluation circuit 2 reaches the set input S of a memory 18 via two inverters 14 and 15 and flips it so that an L signal occurs at the output A 1; on the other hand, a zero signal at output A 0. Because of the extreme narrowness of the pulse, this setting process is prepared by a signal picked up between the reversing stages 14 and 15 , which is fed to a dynamic preparation input V.

A zero signal is present at the output A 0 of the memory 18 after the tilting. Another memory 19 of the same type connected downstream, which has not yet responded, also has a zero signal at output A 1. The normal gate 16 thus receives two zero signals and therefore sends an L signal to the clear input of the memory 18 at its output. Therefore, when a pulse from the clock 10 reaches the preparation input V, the memory 18 flips back to its previous position. The maximum time that can occur until the memory is reset again is equal to the reciprocal value of the pulse frequency of the clock generator 10, i.e. about 3.3 #tsec. It can be expected that no pulse will be delivered by the pulse generator during such a short period of time.

A continuous signal is present at the set input S of the memory 19. When the memory 18 tilts back, the preparation input V is briefly occupied by the edge of the disappearing L signal. The memory 19 therefore tilts into the other position. The L signal thus disappears at its output A 0; If there is also a 0 signal at its other input, an L signal is sent via the normal gate 17 to the clear input of the memory 19. As a result, the memory 19 flips back at the next clock pulse coming from the clock generator 10. The pulses that occur when the memory 19 is tilted back are counted into the binary counter 7 with stages 24, 25 and 26 .

The binary counter 7 is now assigned a logic circuit which detects the flip-flops 24, 25 and 26 with the highest count, forwards this status and then clears this flip-flop again. This circuit is made up of Norgattern 20 to 23 and 27 to 33 .

During the interrogation of the binary counter 7 , an L blocking signal is given to the normal gate 17 . This means that the memory 19 cannot be reset; any incoming impulse thus remains stored in the first memory 18.

It should now be recalled once again that this Actual value memory is a circulating memory in which the value of the individual Places is expressed by their chronological order.

With the binary number query in the binary counter 7 , only the highest digit should be passed on, the other digits must therefore be blocked.

Let it be For example, assuming that the binary stage 26 had responded, its output A 1 would carry an L signal and its output A 0 would have a zero signal. The normal gates 32 and 34 are blocked by the L signal at output A 1.

At the point in time t1 derived from the clock generator 10 , at which the units position appears at the adder-subtractor 11 in the circulating memory, an L signal is sent to the inverter 30 and thus a zero signal is sent to the input of the normal gate 32 . Regardless of whether the output A 0 of the first binary stage 24 carries a zero signal or not, no signal appears at the output of the NOR gate 32 , since this NOR gate 32 is blocked from the output A 1 of the binary stage 26 , which is supposed to carry an L signal.

The same block occurs at time t2 when it is the turn of the second digit. Here, too, the normal gate 34 is blocked by the L signal of the binary stage 26 when a zero signal is briefly given by the clock generator 10 . At time t3 (4th position), the zero signal appearing at the output A 0 of the binary stage 26 and the zero signal supplied by the clock generator are jointly present at the normal gate 35. This then emits an output signal. This means that a zero signal appears at the output of the NOR gate 33 . This zero signal, which serves as a counting pulse, then reaches the adder-subtracter 11 together with the respective signal in the other channel and the relevant location in the circulating memory 12.

As already mentioned, the highest queried binary level must be deleted. Zero signals are present at the NOR gate 28 from the outputs of the NOR gate 20 and 21; the zero signal supplied by the clock generator 10 at the time t4 briefly brings the signal at the output of the normal gate 28 from 0 to L.

As a result of this jump, the binary stage 26 is tilted back, i. H. turned off. The other two stages previously queried at times t 1 and t2, which could then have been deleted at times t2 and t3, remained in their present positions, since their deletion by the L output from output A 1 of binary stage 26 Signal, which is switched to the normal gates 20 and 21, is prevented.

After the binary counter 7 has been queried and cleared, which only takes a short time, the lock on the NOR gate 16 is lifted again. This means that any pulses that may have occurred in the meantime are sent to the binary counter 7.

The circuit described makes it possible to process pulse frequencies of 100 kH, although the adder-subtractor, the actual comparison element, which forms the actual value, only works with a frequency of z. B. 5 kH works.

Claims (2)

Claims: 1. Circuit arrangement for further processing and for comparison, in particular for the formation of the difference between the forward and backward counting pulse sequences supplied by a digital pulse generator for the numerical control of working machines, in which the forward and backward counting pulses each reach an intermediate counter and are here comparable with one another are, d a - characterized in that a one-bit adder-subtractor (11) is provided for comparison, which is located in the circulation path of a circulating memory (12) serving as an actual value memory, and that with each circulation of the memory (12) only that Bit of the highest digit of each counter can be transmitted to the one-bit adder-subtracter and can then be deleted in the intermediate counter (7, 8). 2. Circuit arrangement according to spoke 1, characterized in that the intermediate counters (7, 8) pre-memories (5, 6) are connected upstream, which store the pulses delivered by the pulse generator (1) during the transfer to the comparison element (11). 3. Circuit arrangement according to claim 1 and 2, characterized in that outside the transmission time, the forward and backward pulses are pushed through the pre-storage (5, 6) at the clock frequency of the accident memory (12). 4. Circuit arrangement according to claim 1, characterized in that binary counters are used as the intermediate memory (7, 8).