DE2225462A1 - Method and device for averaging the signals from a forward-backward signal generator - Google Patents

Description

Patent attorneys

The Bendix Corporation Dr. Ing.H. Negendank

'",". , “* * Dipl. Ing.H.Hauck- Dipl. Phys. W.Schmitz

Northern Regional Patent _D £, _{| n} * _{E Graa) fs} . _{Dip | | ng w Wehnert}

Counsel's Office 8 Munich 2, Mozartstrasse 25

jBendix Center l _e l.fon5380586

JSOUTHFIELD, MI 48075 May 16, 1972

United States Attorney File M-2172

Signals.

The invention relates to a method and a device for forming a title value the counting of the signals pending from an up / down signal generator.

j _ i

i "j

■ measuring machines with a decimal display of Koordinatenstellungj a sensor generating position sensors are often exposed to vibrations and \ other disorders, which if not make an accurate reading of decimal difficult if not impossible. These machines are usually shielded and isolated from vibrations that are usually caused by the operation of other neighboring machines, but in many systems these vibrations are not sufficiently damped to accomplish the task fall.

ι ■ j

(In such machines equipped with a position encoder, the two ι Either directional digital impulses, i.e. forward-backward impulses and the one with an up-down counter for counting Ler the corresponding position of the sensor is interconnected,

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According to the previous technology, a circuit for averaging to a pulse counter specially designed for this purpose was usually used for electronic averaging of the counter count coupled, whereupon this mean value was displayed in dec_imal form.

This way has several disadvantages:

1. The one for averaging the total pulse count in the register required circuit is necessarily complicated, relatively expensive and fraught with latent operational uncertainty.

2. Since the circuit for averaging is arranged between the counter and the pulse circuit, normal circuit designs can cause pulses to be lost ¹ that arrive during the averaging.

3. Since the decimal display in such circuit arrangements is normal

sometimes only displays the mean value, the true numerator

was significantly behind the displayed stand. This j is particularly troublesome when the sensor moves in rapid traverse j, the actual count of the pulses changing rapidly.

4. This solution necessarily requires a redesign of the electronic counting and display circuits, which means retrofitting existing systems becomes difficult and expensive.

5. The circuits normally used for averaging in this approach do ^{not average out asymmetrical flutter images 1} correctly.

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6. Since the pulse count of the counter is constantly shifting,

is when the probe is subjected to vibrations · ^ can the timing of the zero or cancellation pulse compared to the phase of the oscillations introduce considerable errors in the subsequent measurement pa.

The object of the invention is thus to provide a device for determining the pulse count of a digital counter create, which essentially avoids these difficulties associated with the previous approaches.

According to the invention, the main counter and the decimal display are on Auxiliary counter connected upstream. Compared to the main counter, the auxiliary counter has a relatively small storage capacity and Pulses from the pulse source reach the auxiliary counter until it is filled in one of the two directions is, whereupon the pulses in this direction are switched through directly to the main counter, as long as the auxiliary counter is in this direction remains filled.

The count contained in the auxiliary counter is called up at regular time intervals, with mean values being periodically formed from these query values and the averaged count then subtracted from the count of the auxiliary counter and added to the main counter. >

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The invention is explained in more detail below. All in the description Features and measures contained may be essential to the invention Be meaning. In the drawings is:

Fig. 1 is a block diagram of the basic arrangement of the invention.

Fig. 2 is a block diagram of a preferred embodiment

the invention.
3 is a circuit diagram of the block diagram shown in FIG.

ges shared synchronizer.
FIG. 3a shows a graph of the pulse profile of the one shown in FIG. 3

Synchronizer.
Fig. 4 is the circuit diagram of a characteristic, shown in Fig. 2 as

Logic circuit shown in the block.
FIG. 5 shows the circuit diagram of the block shown in FIG. 2

Auxiliary counter.
6 shows the circuit diagram of the overflow detector shown as a block in FIG. 2.

7 shows the circuit diagram of the register averaging circuit shown as a block in FIG.
8 shows the circuit diagram of the block shown in FIG. 2

ι, mean value counter.

9 shows the circuit diagram of the block shown in FIG Clock generator and function sequence control.

j FIGS. 10 and 11 are graphs of the timing and function sequence control controlled sequence of different processes. ι

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ORIGINAL INSPECTED

Certain »execution examples are described in more detail below, and for the sake of clarity, certain terminology is used, but it should be noted that this serve only for explanatory purposes and the invention is implemented in many forms of application and exemplary embodiments can be.

In Fig. 1, the per se known position encoder 10 (described in US Pat. No. 2,886,718) indicates pulses. the lines 12, 14-f * the movement steps of the machine probe in the forward or reverse direction.

The pulses applied to lines 12 and 14 reach the gate circuit 16, which they activate depending on the switching state of the Auxiliary counter 24 either directly via lines 20 and 22 to the main counter with display 18 or via lines 26, 28 to the Auxiliary counter 24 forwards.

The auxiliary counter 24 is an up-down counter of relative low storage capacity (for example four 'bits'), its upward counting by the pulses on the line 28 and the countdown of which is controlled by the pulses on line 26.

To differentiate the counting in the auxiliary counter according to the Forward or reverse direction can be a sign flip-flop,

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are provided.

If the count of the auxiliary counter 24 is in the forward or Reverse direction is full, then an overflow signal controls on the line 30, the gate circuit 16, so that a further pulse, which is applied from the lines 12 or 14 ago and the counter reading of the counter 24 would increase beyond its full capacity, via the line 20 or 22 directly to the main counter with display 18 got.

If the auxiliary counter 24 is not fully filled, then the pulse is passed through the gate circuit 16 to it and not to the Main counter with display 18.

The count of the auxiliary counter 24 is periodically determined by the query averaging circuit 32 is tapped, and the mean value of these samples is taken at regular time intervals calculated. There are many known methods for performing this task, and some apparatus using one The interrogation register, accumulator, adder and divider are described in more detail below.

i
The mean of the interrogation values then reaches the pulse generator 34, which emits a pulse count with the correct sign, so that after the next averaging on the lines 36, 38 the average interrogation value is closer to zero and therefore closer to zero

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Counter reading of the main counter with display 18 can be added, while this counting via lines 40, is subtracted from the reading of the auxiliary counter.

The pulse counting can be either from a single pulse or from the whole number of the query mean. In the first case, the circuit required is very simple, but it becomes one requires a relatively large number of averaging cycles, to bring the counter reading of the auxiliary counter to zero. In the second case, the facility needs a maximum of two averaging cycles, but then the required circuit is more complicated.

If the sensor is moved by the operator during operation, then a steady pulse train arrives on one of the two lines 12 or 14 via one of the two lines 26 or 28 to the auxiliary meter 24, until this is filled in one direction or the other, whereupon the overflow signal on line 30 the diversion all further pulses in the direction of the full counter status through the gate circuit 16 directly to the main counter with display 18 causes. Thus, the count displayed during the procedure only rushes by a maximum of the storage capacity of the auxiliary counter after.

If there are no vibrations at the end of this shifting process or other disturbances occur, then the remedy is taken from the

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Read the query values as the full counter reading of the auxiliary counter 24 and added to the status of the main counter with display 18 and from the auxiliary counter 24 either at a rate of one or several pulses per averaging interval or subtracted in total in each averaging interval so that after the real reading value is displayed by the main counter after the actuating time and the counter reading in the auxiliary counter is zero.

If vibrations occur, then the query averaging circuit determines 32 the averaged count, whereupon the pulse generator 34 transfers this value to the status of the main counter 18 and subtracts it from the reading of the auxiliary counter 24 until the averaged count in the auxiliary counter 24 during an averaging interval Is zero. If the decisive factor is there: oscillations of a pulse count within the scope of the storage capacity of the auxiliary counter 24 corresponds, then the main counter with display 18 shows the true mean value according to the position of the sensor the mean value of the pulse count received via the lines 12 and 14, while the auxiliary counter 24 continuously each Pulse received from lines 12 and 14, the query averaging circuit 32 and the pulse generator 34 are ready to update the main counter with display 18 when shifts the mean value count in the auxiliary counter from zero.

Since the true actual count is always the same as the sum of the counts in the main counter with display 18 and in the auxiliary counter 24, can

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the display of the main counter with display 18 opposite the actual count never lag behind by more than the storage capacity of the auxiliary counter 24.

In addition, since the inquiry averaging circuit does the averaging by tapping query values in an averaging interval the true arithmetic mean of the. asymmetrical flutter images.

Another source of error is largely eliminated with the aid of the invention: in a normal installation, the main counter often has to be reset to zero or some other initial value in order to be able to begin with the measurements. If the clear signal is applied at a point in time at which the device is exposed to vibrations and if the signal arrives at the counter, if the count is different from the mean value count corresponding to the oscillation, then the following displays show the error amount, which is the deviation from the mean value Is equivalent to. If ^in: a clear signal on the line 42 to the main counter 18 and the device is exposed to vibrations of the device according to the invention from the signal source 40, then the main counter 18 is unaffected by the phase of the cancellation signal and of the vibrations.

Since no redesign of the main meter or the display is necessary it should also be noted that existing systems simply:

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re-equipped by switching on the device according to the invention between the pulse source and the existing main counter can be.

2 shows the block diagram of a preferred exemplary embodiment of the invention. With this arrangement, the Via the lines 12 and 14 incoming pulses as well as the entire interrogation, averaging and transmission of pulses of the Averaging device synchronized with the main counter by the clock and control circuit 48 and in its sequence controlled to avoid both the need for anti-coincidence switching and critical timing conditions.

The forward and reverse pulses arriving on lines 12 and 14 are converted by the synchronizing device 50 into logic levels, which are generated by the line 56 from the Clock and control circuitry 48 synchronize adjacent clock pulses with the rest of the system operations; this is below explained in more detail.

In this embodiment, the incoming from the position encoder Pulses are not switched through, but the logic levels are combined by the control of the synchronizing device 50 set with the logic levels of other components, i.e. the logic levels of logic circuit 58 for the counting direction, in turn, the transmission of the on lines 56, 60

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from the clock generator and function sequence control 48 are present Controls pulses to the main counter with display 18, the auxiliary counter 24 and the mean value counter 62 described below.

The auxiliary counter 24, which consists of a four-bit up-down counter and the assigned sign of the flip-flop 64,

ί receives pulses at gate circuit 58 via lines 66 and 68, j the forward and forward signals present on lines 12 and 14; Reverse pulses cease until the auxiliary counter 24 has reached its full capacity in either the forward or reverse direction. Now the overflow detector.7 2 transmits a signal with a logic level to the gate circuit 58 via the: line 70A or 70B and thus shows the full count in the forward or backward direction.

; In this case, the gate 58 passes all others

the logic levels connected to the pulses on the lines 12 and 14 in the synchronizing device 50 in the I direction of full capacity, in order to then proceed as in the previous

ι based on the basic arrangement described directly to the main counter ! Display 18 to be transmitted.

The count stored in the auxiliary counter 24 and its sign are periodically transmitted via the lines 74 and 76 to the query means *

; i

; value formation circuit 32 is tapped, stored in an accumulator and added up, and averaged in regular time segments \ , the mean value and its sign after each

I. - 1 2 -

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Averaging interval via lines 80, 82 to the mean value counter 62 and its assigned sign flip-flop 78 is fed.

! These polling, adding and transferring processes are carried out by

'■ Control pulses controlled and synchronized, which are generated by the clock

j and control circuit 48 via lines 84, 88 and 96! lie; this is explained in more detail below.

The mean value counter 62 has a NOR gate with four inputs (described in more detail below), so that a logical input signal ; nal reaches the gate circuit 58 via line 90 when the

; Mean value is not equal to zero, while the logic level of the j flip-flops 78 for the sign or direction of the mean value

is fed via the line 92 of the gate circuit 58. i

Depending on a logic signal present on the line 90 for a value other than zero, the gate circuit 58 controls the clock pulses so that they ^{can be transmitted via the corresponding line of the line pairs 2O un} 22, 66 and 68 as well as 94 and 96 to the Count mean value counting in the main register and count from the auxiliary register 24 and the mean value counter 62, that is, if the mean value counter shows a mean value other than zero and the sign; Flip-flop indicates that the mean value is, for example, in the forward direction, then the gate circuit 58 transmits pulses on the line 20 to the main counter with display 18 and

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^! reverse pulses via lines 68 and 96 until the mean I value counter 62 is counted down to zero, the logic signal on line 90 being blocked for non-zero, and thus a further pulse transmission is interrupted. If the mean value counting corresponds to the opposite direction, "reverse" pulses are fed into the main counter 18 in the same way, while the forward pulses reach the auxiliary counter 24 and the mean value counter.

! The main counter 18 is thus set to the ! brought up to date and the mean value of the counts fed into the auxiliary counter • is kept at zero so that the

! Counting for the correct arithmetic mean on the main counter with j
Display 18 to be able to display.

For a more detailed explanation of the structure and function of the preferred As an embodiment of the invention, a detailed description of the individual components of the block diagram follows of Fig. 2

The circuit diagram of the synchronizer 50 is in detail

shown in fig. i

The forward and reverse pulses present on lines 12 and 14 reach the input T of the two flip-flops A ₁ and A ₉ , so that the falling edge of the via line 12 or

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i14 applied pulse Q of the corresponding flip-flop A high level and Q of the corresponding flip-flop A low level can be.

The next clock pulse applied via line 56, which is fed to the input T of the corresponding "B" flip-flop B ₁ or B ", causes the high-level switching state of IQ and the low-level switching state of Q of flip-flop A. via lines 94, 96, 98 and 100 to inputs J and K of the assigned

! assigned flip-flops B is read in to convert Q or Q of the corresponding

'ends of flip-flops B high or go low will be to let the high-level state so that switching on ein.er ^e Eeitungen 52 or low level and the switching state on one of the lines 52 or 54 is applied.

The absence of a clock pulse (one inverted by 102 Clock pulse) is used to delete the flip-flops A, if one of the flip-flops B by the logical combination of reading the

OR-

Signal state of 5 2 and 54 in the gate 104 via the lines 1106, 108 with the feed of the output signal of the OR gate in the AND gate 110 was turned on, the inverted absence of the clock pulse is present on line 112. This ensures that the flip-flops A the flip-flops B before Deletion can be read.

Since the flip-flops A have now been erased, the next one also erases

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- 15 clock pulse the flip-flop B.

Thus, an input pulse on one of the lines 12 or 14 results in a change in the switching state on one of the lines 52 (and 1Γ2) or 54 (and 5T) in sync with the clock pulses and from a duration of a clock cycle, whereby the correct function of the logic gate circuit is ensured.

Fig. 3a shows this in the form of a curve.

In F.ig. 4 shows the circuit diagram of the logic circuit 58, i

j As described above, the gate circuit 58 controls the upper, transmission of the clock pulses present on the line 56 to the main counter 18 via the lines 20, 22 to the auxiliary counter 24

via lines 66 and 68 and to the mean value counter 6 2

via lines 94, 96. In the exemplary embodiment of the invention described here, this is done by entering the clock pulses to the input of a series of AND gates 114, 116, 118, 120, 122 and 124, with the input from lines 126, 128, 130, 132, 134 and 136 tapped logic signals are present. If the logical target voltage level prevails on these lines, then the UHD gates are switched on and an impulse is generated can get to his appropriate line. As some of the '

turned devices from lines 66, 68, and 94 and 96

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require low level pulses, these pulses are inverted for this purpose.

The circuit of AND and OR gates shown in the left part of FIG. 4 and that of the AND gates described is a charac-

Iteristic device implementation of the logic circuits, which generate the correct impulses and transmit them to the corresponding lines as follows:

Line 94 (mean value counter 62 up): A pulse is generated when the following processes take place: The mean value counter 62 shows a mean value UND backwards, the OR gate 54 shows a countdown, the AND gate 5 2 does not count up, and;

the overflow detector 72 as well as the line 52 an overflow not j forward.

Line 96 (mean value counter down): A pulse is generated! when the following processes take place: An AND gate indicates an upward mean value, the OR gate 52 an upward count, the AND gate 54 does not count down, and the overflow detector 72 and line 5-4 do not overflow.

Line 20 (main counter up): A pulse is generated when a pulse is to be applied to line 96, OR an up count indicated on line 52 AND a forward over;

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I run indicated by the overflow detector 72 and the flip-flop 64 will.

I Line 22 (main counter down): A pulse is generated when ! a pulse should be present on line 94 OR a reverse

count is displayed on line 54 AND an overflow backwards indicated by overflow detector 72 and flip-flop 64 will.

! Line 66 (auxiliary counter up): A pulse is generated if

j an up count is displayed on line 52 AND on the ι Line 20 should not have a pulse OR no down counting is displayed on ΊΓΪ AND there is a pulse on line 94

SOlI. :

Line 68 (auxiliary counter down): A pulse is generated when a down counting is displayed on line 54 AND no pulse is to be present on line 22 OR no up counting is displayed on line TI AND line 96 is to receive a pulse.

The logic circuit shown is of the NAND-NOR type, ium Zweck-ί from the

Usually the auxiliary counters 24 and the mean value counter 62 are required to emit low-level impulses.

It can be seen that these circuits are responsible for the overflow process as well

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ensure that the mean value is updated using the above of the block diagram of FIG. 2 have been written.

| Fig. S shows the auxiliary counter 24, which consists of the binary four-bit up-down counter 138 exists on the count-up pulses on forward line 66 and reverse counts on the reverse line 68 are present. The upward counting is done by binary counting, while the countdown is in a two's complement of the Binary counting takes place.

; When the counter 138 is in the 0000 state and a pulse j appears on line 68, then counter 138 generates one jimpuls for a subtraction carry on line 140 while in switching state 1111 and when a pulse is applied to line 66, an addition carry pulse is generated on line 142 as it corresponds to the state of the art.

The addition and subtraction carry pulses reach the flip-flop 64, so that the line 152 goes high when a Pulse on line 140 and low level when a pulse occurs on line 142, so that the high level Switching state of line 152 (or the low level switching state of 15 2) a positive or zero count in counter 138 indicates, while the low level switching state of line 152 (or a high level state on line 152) a indicates negative count.

This logical signal is used to generate an overflow detector

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signal and the mean value counts will be explained in more detail below.

The count of the auxiliary counter 24 is continuously indicated by the number shown in FIG ^ overflow detector 72 shown monitored from the binary four-bit comparison device 144 and the two coupled NAND-I ports 146, 148. One side of the comparator is connected via lines 76 and 150 to the output of the counter, while the bit of the lowest digit is in the other four-bit input connected to the logical 'one' and the other three higher-order bits via the line 74 to the line 152 so that if the logic signal is high on line 152 for a zero or positive count in 138 of FIG Count is compared with the binary number 11.11 = +15 and at I the count with a low-level signal on the line 152; ! the binary number 0001 is compared, which is the two's complementary for '

represents a -15. I.

Thus when the counter 138 is replenished in either direction then a high level signal is present on lines 154 and 156 and generates a low level output signal at 70A, if it is padded in the positive direction (since then 152 is high) or a low output on 70B if it is padded in the reverse or negative direction (since then J4-5-2 is high).

I!

! Under all other conditions, lines 7OA and 7OB '

! high level, so that a low level signal at 70A indicates! ¹ -20- i

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that the counter 138 overflows in the forward direction and a low level Signal on line 7OB reports an overflow in the reverse direction. These signals are used to control the transmission ! Generation of the clock pulses, as described above with the aid of the logic gate circuit 58 was described.

; Fig. 7 shows the details of the query averaging

circuit 32 of the preferred embodiment of the invention.

This arrangement comprises a five-bit shift register 160, on which the counting of the auxiliary counter is in parallel at the inputs Aq, A-, A- and A- and the sign on line 152 am Input A. is present when a control pulse on line 162 from

j of the clock and function sequencer 48 is received. This count is then serially added to accumulator 164, which is on the two interconnected eight-bit shift registers j 166 and 168 which form a sixteen-bit shift register.

! The shift of registers 160, 166 and 168 is done by pulses j controlled via line 170 from circuit 48

■ lie while the addition is carried out by the adder 172

ι is whose Addit_ionsübert due the in J-K flip-flop 174 get saved. To practically add the contents of the five-bit shift register 160 into the sixteen-bit accumulator 164 can, the flip-flop for the highest place value, in which the sign is entered via line 152, to the serial input of the shift register 160 via the line 176 switched. Thus the correct places become higher order auotmatically the accumulator 164 in shifts above the

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fourth flip-flop, i.e. zeros for binary up-counts and one he for countdowns in the form of complementary Two, in which the countdowns from the auxiliary

j counter 24 can be received as described above.

The scan register 160 is then cleared by a signal sent on line 178 from the timer and function sequence control young 48 is applied, whereupon the cycle repeats.

At the end of an averaging or averaging cycle j successively entered 128 sample values into the scan register 160

• and added to the accumulator 164, so that the slider

igister 166 and 168 contain the sum of the 128 query values.

[ The number 128 for the query values was chosen because it

'7

ί is a power of 2 (2) and therefore by shifting the sum can easily be averaged by seven binary digits to the right, which is achieved in the exemplary embodiment of the invention,

j. that the four flip-flops in the accumulator 164 are read out via the lines j by seven positions offset to the left. The j sign of the mean value can be read as one of the higher order bits to the left of the mean value flip-flops on line 82, since the higher order bits are either a total of j units and thus indicate a binary two's complementary number or a downward counting or counting down. Represent zeros and ^{indicate a 1} binary positive count and an up count. j

Thus, at the end of the averaging cycle ^1, the

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Line 80 read out mean value counting and the sign read out via line 82 are input to mean value counter 62 and the associated sign flip-flop 78, the accumulator then being cleared by a signal that is sent from circuit 48 in preparation for a new averaging cycle the line 180 is present.
j

{Fig. 8 shows the details of the mean counter 62 as well as the

! of its associated sign flip-flop 78. The mean value counter & 2 consists of a four-bit up-down counter 182 whose Inputs are routed to lines 80 and the outputs of which are connected to a NOR gate 184 equipped with four inputs, sojdaß a logic one is present on line 90 when there is no count in counter 182, thereby eliminating the foregoing Non-zero signal is emitted. The register is counted up when pulses are received on line 84 (up) and down counting when received on line 96 Impulses as described above.

The over the line 185 from the clock generator and function sequence

Control signal received "Mandatory zero ^11" is present at the NOR gate 184 during the data transmission in order to prevent a false display by the logic circuit 58.

The sign fed to the flip-flop 78 causes a high-level signal on line 92 and a low-level signal on line Wl when counting up in the mean value register and a low-level signal on line 92 and a high-level signal.

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level signal on line 92 when counting down in Mean value register 62, these signals of the logic circuit

■ d / 58 are fed in to control the clock pulses, as above

was written.

^] The clock and function sequence control 48 is in its individual. 9 and contains the square-wave pulse source 186 divided by the flip-flop, the pulse frequency on j of the line 56 being selected to be far above the maximum pulse frequency applied by the position sensor in order to ensure the correct work and function of the logic circuit 58 Guarantee ZM . In the preferred embodiment, the frequency of the source 186 was about 12 Mhz, so that after division by the flip-flop 188 and the AND gate 189 a 6 Mhz clock pulse is present on the line.

In order to control the query averaging circuit, this pulse train is passed on from the monostable multivibrator 190 and the shift register 192 existing arrangement divided down.

The shift input of the shift register is led to the output Q via line 194 of the shifted flip-flop 188, so that it is shifted with an oscillation frequency of 6 Mhz?

; The false output 4 of the monostable multivibrator 190 is on '

; the serial input of the shift register 192, so that '

^! in the initial clear state a "one" to the flip-flop via - -,.

' -24-!

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is fed to pin 3 of shift register 192 ^ the one-shot

Multivibrator is activated directly by transition 0-1 of the flip ' Flops triggered by pin 3 via line 196, so that the

False output 4 is low for the duration of a pulse of the monostable j multivibrator and thus prevents

j further counts during the unstable period

i
Register 192 must be entered. Thus, the "one" in the flip-flop propagates backwards and outputs a sequential clock signal to pins 5, 10, 12 and 13 to control the averaging circuit.

; After the monostable multivibrator 190 becomes stable again, j, a "one" appears again at incorrect output 4 and the cycle! repeated. A change in the values of the RC circuit 191 ι causes a change in the period of one pulse, which results in a change in the time interval of the query, i.e. in the Scanning speed. This allows the scanning speed to be adapted to the frequency of disturbances in a particular system will.

The three four-8-bit binary counters 198, 200 and 202 are used for counting the shifting and adding operations of the query averaging circuit 32. The pulse from pin 3 of shift register 192 comes on line 204 to line 170 and causes the shift of the shift register described below, and each such pulse is sent to counter 198 via line 206 entered a count to count the shifts. After 1.5 shifts, the next pulse of the counter represents 198

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return all bits to zero, and this state is indicated by the AND gate 208 tapped, as a result of which a high-level signal is present on line 210 after 16 shifts, which after switching on on the sequential control pulse from pin 5 of the AND gate • 212 generates a reverse glitch on line 178 to

j to clear scan register 160 (Fig. 7).

! The sixteenth shift signal on line 210 is in the AND gate 214 also a control pulse from pin 10 and a 12 Mhz clock pulse of source 186 is coupled to on line 216 not to generate a low-level signal, which in turn is transmitted via the Line 218 the output signal Q of the .Flip-Flop 188 to AND gate ! 22O is turned off, so that a high level Impulse arises when the AND gate 220 is activated. This

j pulse triggers data transmission from the auxiliary counter to the sampling register 160 off. It is optionally timed to ensure data transmission in the stable state of the auxiliary meter perform (not during the change of state).

The sixteenth pulse also generates a carry pulse on line 222 to enter a count into counter 200, the is coupled to counter 202 by transmission line 224. ι Thus, sixteen shifts for an addition

j "

: Cycle counted in the interconnected counters 200 and 202,

ι been

j until the 128 query values have been tapped. The 128th query has the effect that the bit on 'pin 11 of counter 202 ^{becomes' one 1} , which on the one hand clears all three counters and

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on the other hand, a logical input signal on line 228 and a control signal (forced zero) on line 185 (through 230 inverted) reaches the AND gate 226.

A sequence control pulse from pin 10 of shift register 192 is switched to the AND gate 226 to send a control signal to the Lines 86 and 88 deliver. This signal is the shifted Transfer mean value to mean value counter 6 2.

The bit signal of pin 11 is applied to a sequence control pulse from! Pin 12 of shift register 192 in AND gate 232, To generate the clear signal C on line 180.

jThe clock generated by the function sequence control signals and Sequence control signal is shown as a graph in Figures 1o and shown.

Fig. 10 shows the shift S, the erasure of the scanner register R and the transmission T of the pulses when they occur in each of the 128! Addition cycles, while FIG. 11 shows the details of the j represents function sequence control at the end of the 128th addition cycle,

In addition to the exemplary embodiments described above, further holes are possible without departing from the scope of the invention.

For example, the synchronizer and the logical Replaced signals for the counting pulses by an arrangement

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in which a pulse counting circuit with anti-coincidence circles is coupled to the pulse sum node.

! Of course, the logical implementation of the switching function is at ! Both solutions with the most diverse variations of device-technical parts possible, as it corresponds to the state of the art.

As described above, the mean value of the sample values taken from the {count in the auxiliary counter can be used instead of in a single cycle (as described in the exemplary embodiment) is added to the main register in a series of determination cycles and can be subtracted from the auxiliary counter.

! Of course, arithmetic operations like the ! Addition, division, etc. can be carried out with a wide variety of calculation methods and are not based on the one described above Procedure bound. '

Although the invention has been described using the position encoder of a measuring machine every counter with bidirectional signals, i.e. with up and down counting, can use the principles use the invention to advantage.

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Claims (17)

The Bendix Corporation Northern Regional Patent! Counsel's Office Bendix Center May 17, 1972 $ outhfield, Mich. 48075, USA Lawyer File M-2172 Pat | ntans2rüche_ 1. Method for averaging the count of signals from a bidirectional signal source, characterized in that it comprises the following method steps: counting of the signals in a first counter until its storage capacity is full and further signals are no longer counted in either of the two directions counting of all additional signals in a second counter, averaging of that contained in the first counter Count in a time interval and periodic updating of the count of the second counter by changing this count to reflect the mean value count established during the mean value formation. 2. The method according to claim 1, characterized in that in the 'averaging query values from the count in the first counter can be tapped in a time interval and the mean value is formed from the count of these query values. 3. The method according to claim 1, characterized in that the counting in the second counter in the direction of averaging of the mean value is changed and that the count in the first 209851/1186 - 29 counter is changed in the opposite direction to this mean value. ^! 4. The method according to any one of the preceding claims, characterized in that that the length of the time interval can be chosen differently in which the mean value of the first counter is tapped. ' 5. Averaging digital counter for calculating the net count of signals from a bidirectional signal source according to the method of claims 1 to 4, characterized by the following assemblies: a first up / down counter (24) of limited storage capacity and a second up / down counter (18), both of which are bidirectional Signal source (10) are connected via a synchronization device (50) and a gate circuit (16, 58), a Overflow connection (30, 72) between the first meter (24) and the gate circuit (16, 58), as well as a circuit with an averaging circuit for the interrogation values (32) and a Pulse generator (34, 62) between the output of the first! Counter (24) and the gate circuit (16, 58), all modules being controlled by a clock and sequence control (48) will. 6. Digital counter according to claim 5, characterized in that the: j bidirectional signal source (10) is a position sensor,. which generates pulses as a function of the movement of a probe j in the forward or reverse direction. -30- 209851/1186 7. Digital counter according to claim 5 or 6, characterized in that the synchronizing device (50) comprises the following assemblies: a first pair of flip-flops (A ₁ A ₂ ) and a second pair of flip-flops (BB,), wherein the outputs of the first pair of flip-flops are led to the inputs of the second pair of flip-flops and the inputs of the first pair of flip-flops are connected to the bidirectional signal source (10) (12, 14), the inputs of the The second pair of flip-flops are connected in parallel to the clock and sequence control (48) and the outputs of the second pair of flip-flops are connected accordingly to the gate circuit (48) (52, "51, 54, 54). 8. Digital counter according to claim 7, characterized in that the clear outputs (Q) of the second flip-flop pair (B ₁ B ₉ ) with the clear inputs of the first flip-flop pair (A ₁ A ₇ ) via one of the OR Gate (104) and the AND gate (110) formed series circuit are connected, wherein the second input of the AND gate is led via the inversion circuit (102) to the clock generator and function sequence control (48). 9. Digital counter according to one of claims 5 to 8, characterized in that that the gate circuit (16, 58) performs the following control functions: Transmission of the over the line (56) from the clock generator and function sequence control (48) pending clock pulses to the second counter (18), Control of the first counter (24) and the pulse generator or mean value counter (62) via the lines (20, 22; 66, 209851/1186 68; 94, 96) by feeding the clock pulses into an input: a number of AND gates (114, 116, 118, 120, 122, 124), the second input sampling the logic signals on those associated with the synchronizer (50) j lines (126, 128, 130, 134, 136) are located, as well as control > the overflow detector (72) and the mean value counter (62, 78) 'via a logic circuit of the NAND-NOR type. 10. Digital counter according to claim 5, characterized in that the first up / down counter (24) is a binary up / down counter (138) and a flip-flop (64) connected to the two outputs (13, 12) of the binary counter. 11. Digital counter according to claim 5 and 10, characterized in that the overflow detector (7 2) consists of one with two NAND gates (146, 148) coupled binary comparison device (144) consists that one side of the comparison device (10-13) is connected the output (150) of the first counter (24), while the bit for the last digit (4) at the other input (1-4) is connected to the logical one and the three higher-order bits (1-3) to an output (152) of the flip-flop (64) are led. 12. Digital counter according to one of claims 5 to 11, characterized in that that the query averaging circuit; (32) comprises the following assemblies: a shift register (160), which shows the count of the first counter (24) in parallel: 2 0 9 8 5 1/1 1 B 6 at a number of inputs (A _Q - A-) and receives the sign at another input (A.) from the second output (152) of the flip-flop (64), an accumulator (164) for the serial addition of this count Adding unit (172) and a flip-flop (174) for storing the carries, the function of the query averaging circuit (32) being controlled by pulses that are applied from the clock generator and function sequence control (48) (162, 170, 178, 180), as well as j in that a certain number of outputs (80, 8 2) I of the accumulator as inputs to the mean value counter or Pulse generator (62) and its associated sign, transmitter (78) are performed. ; 5 13. Digital counter according to Claim 12, characterized in that the mean value counter or pulse generator (34, 62) has an up / down counter (182) includes whose inputs with the outputs (8o) of the accumulator (164) and its outputs with are connected to the NOR gate (184) which has as many inputs as the bit number of the counter (182), such as by the up-down counter (18 2) is assigned a sign flip-flop (78) which is connected to an output (8 2) of the accumulator (164) is connected. 14. Digital counter according to claim 13, characterized in that j the NOR gate (184) through a line (185) for a control signal "forced zero" with the clock generator and function sequence control (48) is connected. -33- 2 0 9 8 5 1/118 6 15. Digital counter according to one of claims 5 to 14, characterized in that the clock generator and function sequence control comprises the following assemblies: a by a first flip-flop (188) divided source of wave pulses (186), the one first pulse train (56) of a first specific frequency generated and by the application of a pulse (190) of the monostable shift register (192) controls the query averaging circuit (32, 34, 62, 78), the shift input of the shift register (192) is connected to the clear output Q of the first flip-flop (188). 16. Digital counter according to claim 15, characterized in that an RC circuit (191) between the outputs of the monostable Shift register (190) is connected to a setting of the allow monostable pulse. 17.Digital counter according to claim 15 or 16, characterized in that that the clock and function sequence control (48) comprises three binary four-bit counters (198, 200, 202) to the shift and counting additions of the interrogation averaging circuit (32). 209851/1186 « ³ V Read if e