DE10251881A1 - Abtastmultiplikation - Google Patents

Abtastmultiplikation

Info

Publication number
DE10251881A1
DE10251881A1 DE10251881A DE10251881A DE10251881A1 DE 10251881 A1 DE10251881 A1 DE 10251881A1 DE 10251881 A DE10251881 A DE 10251881A DE 10251881 A DE10251881 A DE 10251881A DE 10251881 A1 DE10251881 A1 DE 10251881A1
Authority
DE
Germany
Prior art keywords
tester
state data
multiplexed
cycle
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10251881A
Other languages
German (de)
English (en)
Inventor
Stuart L Whannel
Garrett O'brien
John Stephen Walther
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE10251881A1 publication Critical patent/DE10251881A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE10251881A 2001-11-09 2002-11-07 Abtastmultiplikation Withdrawn DE10251881A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/007,825 US6865704B2 (en) 2001-11-09 2001-11-09 Scan multiplexing for increasing the effective scan data exchange rate

Publications (1)

Publication Number Publication Date
DE10251881A1 true DE10251881A1 (de) 2003-06-18

Family

ID=21728306

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10251881A Withdrawn DE10251881A1 (de) 2001-11-09 2002-11-07 Abtastmultiplikation

Country Status (4)

Country Link
US (1) US6865704B2 (enExample)
JP (1) JP2003194883A (enExample)
DE (1) DE10251881A1 (enExample)
GB (1) GB2386693B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7404109B2 (en) * 2003-06-12 2008-07-22 Verigy (Singapore) Pte. Ltd. Systems and methods for adaptively compressing test data
US7010453B2 (en) * 2003-10-14 2006-03-07 Agilent Technologies, Inc. Methods and apparatus for optimizing lists of waveforms
US6944558B2 (en) * 2003-10-14 2005-09-13 Agilent Technologies, Inc. Methods and apparatus for optimizing the masking of waveforms to reduce the number of waveforms in a list of waveforms
KR100736673B1 (ko) * 2006-08-01 2007-07-06 주식회사 유니테스트 반도체 소자 테스트 장치
US8694845B2 (en) * 2010-04-25 2014-04-08 Ssu-Pin Ma Methods and systems for testing electronic circuits
US11782092B1 (en) 2022-05-18 2023-10-10 Stmicroelectronics International N.V. Scan compression through pin data encoding
US12480993B2 (en) 2024-03-18 2025-11-25 Stmicroelectronics International N.V. Low pin count scan with no dedicated scan enable pin

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433414A (en) * 1981-09-30 1984-02-21 Fairchild Camera And Instrument Corporation Digital tester local memory data storage system
US4652814A (en) * 1983-06-13 1987-03-24 Hewlett-Packard Company Circuit testing utilizing data compression and derivative mode vectors
DE3515802A1 (de) * 1985-05-02 1986-11-06 Siemens AG, 1000 Berlin und 8000 München Anordnung zur schnellen erzeugung von grossen pruefdatenwortmengen in einer pruefeinrichtung
US5127011A (en) 1990-01-12 1992-06-30 International Business Machines Corporation Per-pin integrated circuit test system having n-bit interface
US5825785A (en) * 1996-05-24 1998-10-20 Internaitonal Business Machines Corporation Serial input shift register built-in self test circuit for embedded circuits
DE19781186T1 (de) * 1996-10-15 1998-12-17 Advantest Corp Speichertestgerät und Verfahren zum Umschalten des Geräts zwischen einem RAM-Testmodus und einem ROM-Testmodus
US6067651A (en) * 1998-02-20 2000-05-23 Hewlett-Packard Company Test pattern generator having improved test sequence compaction
JP4121634B2 (ja) * 1998-09-21 2008-07-23 株式会社アドバンテスト メモリ試験装置

Also Published As

Publication number Publication date
GB0224890D0 (en) 2002-12-04
GB2386693B (en) 2005-07-20
JP2003194883A (ja) 2003-07-09
US6865704B2 (en) 2005-03-08
GB2386693A (en) 2003-09-24
US20030093731A1 (en) 2003-05-15

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE) PTE. LT

8139 Disposal/non-payment of the annual fee