DE102018106863A1 - Speichersystem zum Unterstützen einer internen DQ-Terminierung eines Datenpuffers - Google Patents

Speichersystem zum Unterstützen einer internen DQ-Terminierung eines Datenpuffers Download PDF

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Publication number
DE102018106863A1
DE102018106863A1 DE102018106863.8A DE102018106863A DE102018106863A1 DE 102018106863 A1 DE102018106863 A1 DE 102018106863A1 DE 102018106863 A DE102018106863 A DE 102018106863A DE 102018106863 A1 DE102018106863 A1 DE 102018106863A1
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DE
Germany
Prior art keywords
internal
memory module
data
memory
termination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102018106863.8A
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German (de)
English (en)
Inventor
Sun-Young Lim
Hui-chong Shin
In-su Choi
Young-Ho Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020170102574A external-priority patent/KR102400102B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102018106863A1 publication Critical patent/DE102018106863A1/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE102018106863.8A 2017-05-11 2018-03-22 Speichersystem zum Unterstützen einer internen DQ-Terminierung eines Datenpuffers Pending DE102018106863A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20170058904 2017-05-11
KR10-2017-0058904 2017-05-11
KR10-2017-0102574 2017-08-11
KR1020170102574A KR102400102B1 (ko) 2017-05-11 2017-08-11 데이터 버퍼의 내부 데이터(dq) 터미네이션을 지원하는 메모리 시스템

Publications (1)

Publication Number Publication Date
DE102018106863A1 true DE102018106863A1 (de) 2018-11-15

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ID=63962703

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102018106863.8A Pending DE102018106863A1 (de) 2017-05-11 2018-03-22 Speichersystem zum Unterstützen einer internen DQ-Terminierung eines Datenpuffers

Country Status (4)

Country Link
US (2) US10496584B2 (https=)
JP (1) JP7173751B2 (https=)
CN (1) CN108874306B (https=)
DE (1) DE102018106863A1 (https=)

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US10831963B1 (en) * 2017-08-26 2020-11-10 Kong-Chen Chen Apparatus and method of parallel architecture for NVDIMM
US11537521B2 (en) * 2019-06-05 2022-12-27 Samsung Electronics Co., Ltd. Non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM
CN112817884B (zh) * 2019-11-15 2025-04-04 安徽寒武纪信息科技有限公司 一种存储器以及包括该存储器的设备
CN111045955B (zh) * 2019-12-16 2023-09-22 瓴盛科技有限公司 架构动态配置的存储装置及其操作方法及电子设备
CN113360430B (zh) * 2021-06-22 2022-09-09 中国科学技术大学 动态随机存取存储器系统通信架构
US12554633B2 (en) * 2024-01-29 2026-02-17 SanDisk Technologies, Inc. Non-target on-die termination

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JP3799251B2 (ja) 2001-08-24 2006-07-19 エルピーダメモリ株式会社 メモリデバイス及びメモリシステム
KR100606242B1 (ko) * 2004-01-30 2006-07-31 삼성전자주식회사 불휘발성 메모리와 호스트간에 버퍼링 동작을 수행하는멀티 포트 휘발성 메모리 장치, 이를 이용한 멀티-칩패키지 반도체 장치 및 이를 이용한 데이터 처리장치
KR20060031109A (ko) 2004-10-07 2006-04-12 삼성전자주식회사 멀티 랭크 메모리 시스템 및 이를 위한 메모리 랭크별 온다이 터미네이션 저항 조절 방법
US7479799B2 (en) 2006-03-14 2009-01-20 Inphi Corporation Output buffer with switchable output impedance
US7486104B2 (en) 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
US7716411B2 (en) * 2006-06-07 2010-05-11 Microsoft Corporation Hybrid memory device with single interface
KR100790821B1 (ko) * 2006-11-15 2008-01-03 삼성전자주식회사 반도체 메모리 장치에서의 온다이 터미네이션 회로
US8301833B1 (en) * 2007-06-01 2012-10-30 Netlist, Inc. Non-volatile memory module
US8874831B2 (en) * 2007-06-01 2014-10-28 Netlist, Inc. Flash-DRAM hybrid memory module
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KR101841622B1 (ko) * 2010-11-04 2018-05-04 삼성전자주식회사 온-다이 터미네이션 회로를 가지는 불휘발성 메모리 장치 및 그것의 제어 방법
US9158726B2 (en) * 2011-12-16 2015-10-13 Inphi Corporation Self terminated dynamic random access memory
US9747230B2 (en) 2012-10-15 2017-08-29 Rambus Inc. Memory rank and ODT configuration in a memory system
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Also Published As

Publication number Publication date
CN108874306A (zh) 2018-11-23
JP2018190401A (ja) 2018-11-29
CN108874306B (zh) 2022-08-16
JP7173751B2 (ja) 2022-11-16
US20180329850A1 (en) 2018-11-15
US10684979B2 (en) 2020-06-16
US20200065289A1 (en) 2020-02-27
US10496584B2 (en) 2019-12-03

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