DE102005051479A1 - Speichersystem und Schnittstellen-Zeitsteuerverfahren - Google Patents
Speichersystem und Schnittstellen-Zeitsteuerverfahren Download PDFInfo
- Publication number
- DE102005051479A1 DE102005051479A1 DE102005051479A DE102005051479A DE102005051479A1 DE 102005051479 A1 DE102005051479 A1 DE 102005051479A1 DE 102005051479 A DE102005051479 A DE 102005051479A DE 102005051479 A DE102005051479 A DE 102005051479A DE 102005051479 A1 DE102005051479 A1 DE 102005051479A1
- Authority
- DE
- Germany
- Prior art keywords
- memory
- information
- control circuit
- signal
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040085381A KR100564635B1 (ko) | 2004-10-25 | 2004-10-25 | 메모리 모듈 내에서의 인터페이스 타이밍을 제어하는메모리 시스템 및 그 방법 |
| KR10-2004-0085381 | 2004-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102005051479A1 true DE102005051479A1 (de) | 2006-05-24 |
Family
ID=36207349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102005051479A Ceased DE102005051479A1 (de) | 2004-10-25 | 2005-10-25 | Speichersystem und Schnittstellen-Zeitsteuerverfahren |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7421558B2 (https=) |
| JP (1) | JP5068444B2 (https=) |
| KR (1) | KR100564635B1 (https=) |
| DE (1) | DE102005051479A1 (https=) |
Families Citing this family (53)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
| US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
| US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
| US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
| US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
| US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
| US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
| US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
| US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
| US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
| US7515453B2 (en) * | 2005-06-24 | 2009-04-07 | Metaram, Inc. | Integrated memory core and memory interface circuit |
| US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
| US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
| US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
| US7580312B2 (en) * | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
| US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
| US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
| US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
| US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
| US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
| US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
| US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
| US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
| US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
| US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
| US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
| US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
| US7590796B2 (en) | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
| US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
| US7472220B2 (en) * | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
| KR101303518B1 (ko) | 2005-09-02 | 2013-09-03 | 구글 인코포레이티드 | Ｄｒａｍ 적층 방법 및 장치 |
| US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
| US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
| US7724589B2 (en) * | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
| US7516293B2 (en) * | 2006-09-08 | 2009-04-07 | International Business Machines Corporation | Increased performance using mixed memory types |
| DE102007010284A1 (de) * | 2007-03-02 | 2008-09-04 | Qimonda Ag | Schnittstellenvorrichtung, Schaltungsmodul, Schaltungssystem, Vorrichtung für eine Datenkommunikation und Verfahren zum Kalibrieren eines Schaltungsmoduls |
| US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
| US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
| TW200915176A (en) * | 2007-09-19 | 2009-04-01 | Asustek Comp Inc | Method for setting actual operation frequency of memory and setting module thereof |
| JP5292978B2 (ja) * | 2008-08-01 | 2013-09-18 | 富士通株式会社 | 制御装置、情報処理装置、及びメモリモジュール認識方法 |
| US8018753B2 (en) * | 2008-10-30 | 2011-09-13 | Hewlett-Packard Development Company, L.P. | Memory module including voltage sense monitoring interface |
| EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
| US8730758B2 (en) * | 2009-06-24 | 2014-05-20 | Advanced Micro Devices, Inc. | Adjustment of write timing in a memory device |
| US8489912B2 (en) * | 2009-09-09 | 2013-07-16 | Ati Technologies Ulc | Command protocol for adjustment of write timing delay |
| CN102129414B (zh) * | 2010-01-15 | 2013-12-04 | 华为技术有限公司 | 一种变频总线适配器、适配方法及系统 |
| KR20120121231A (ko) * | 2011-04-26 | 2012-11-05 | 삼성전자주식회사 | 메모리 장치 및 메모리 시스템 |
| KR20140086672A (ko) | 2012-12-28 | 2014-07-08 | 에스케이하이닉스 주식회사 | 메모리와 컨트롤러 사이의 데이터 통신 방법 및 그를 이용한 반도체 시스템 |
| KR102120825B1 (ko) * | 2013-01-03 | 2020-06-09 | 삼성전자주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
| US20150347151A1 (en) * | 2014-05-28 | 2015-12-03 | Diablo Technologies Inc. | System and method for booting from a non-volatile memory |
| KR20160120004A (ko) | 2015-04-07 | 2016-10-17 | 삼성전자주식회사 | 시스템 온-칩 및 이를 포함하는 전자 기기 |
| US10592114B2 (en) | 2016-03-03 | 2020-03-17 | Samsung Electronics Co., Ltd. | Coordinated in-module RAS features for synchronous DDR compatible memory |
| US9830086B2 (en) * | 2016-03-03 | 2017-11-28 | Samsung Electronics Co., Ltd. | Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group |
| US10558388B2 (en) * | 2016-03-03 | 2020-02-11 | Samsung Electronics Co., Ltd. | Memory system and method of controlling the same |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6646953B1 (en) * | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
| TW451193B (en) * | 1999-11-30 | 2001-08-21 | Via Tech Inc | A method to determine the timing setting value of dynamic random access memory |
| US6535411B2 (en) * | 2000-12-27 | 2003-03-18 | Intel Corporation | Memory module and computer system comprising a memory module |
| US20020144173A1 (en) * | 2001-03-30 | 2002-10-03 | Micron Technology, Inc. | Serial presence detect driven memory clock control |
| JP3588599B2 (ja) * | 2001-07-05 | 2004-11-10 | 株式会社東芝 | 半導体バッファ能力調整方法、半導体バッファ能力調整システム、及び半導体装置 |
| GB0123422D0 (en) * | 2001-09-28 | 2001-11-21 | Memquest Ltd | Improved memory controller |
| US20030105932A1 (en) * | 2001-11-30 | 2003-06-05 | David Howard S. | Emulation of memory clock enable pin and use of chip select for memory power control |
| US20050041453A1 (en) * | 2003-08-22 | 2005-02-24 | Brazis Paul W. | Method and apparatus for reading and writing to solid-state memory |
| US20050190193A1 (en) * | 2004-03-01 | 2005-09-01 | Freker David E. | Apparatus and a method to adjust signal timing on a memory interface |
| US7222224B2 (en) * | 2004-05-21 | 2007-05-22 | Rambus Inc. | System and method for improving performance in computer memory systems supporting multiple memory access latencies |
-
2004
- 2004-10-25 KR KR1020040085381A patent/KR100564635B1/ko not_active Expired - Fee Related
-
2005
- 2005-10-24 US US11/256,108 patent/US7421558B2/en active Active
- 2005-10-25 JP JP2005310377A patent/JP5068444B2/ja not_active Expired - Fee Related
- 2005-10-25 DE DE102005051479A patent/DE102005051479A1/de not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JP5068444B2 (ja) | 2012-11-07 |
| US7421558B2 (en) | 2008-09-02 |
| US20060090054A1 (en) | 2006-04-27 |
| JP2006127515A (ja) | 2006-05-18 |
| KR100564635B1 (ko) | 2006-03-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| R016 | Response to examination communication | ||
| R002 | Refusal decision in examination/registration proceedings | ||
| R003 | Refusal decision now final | ||
| R003 | Refusal decision now final |
Effective date: 20141128 |