DE102004015862A1 - Verfahren zur Herstellung einer leitenden Barrierenschicht in kritischen Öffnungen mittels eines abschließenden Abscheideschritts nach einer Rück-Sputter-Abscheidung - Google Patents

Verfahren zur Herstellung einer leitenden Barrierenschicht in kritischen Öffnungen mittels eines abschließenden Abscheideschritts nach einer Rück-Sputter-Abscheidung Download PDF

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Publication number
DE102004015862A1
DE102004015862A1 DE102004015862A DE102004015862A DE102004015862A1 DE 102004015862 A1 DE102004015862 A1 DE 102004015862A1 DE 102004015862 A DE102004015862 A DE 102004015862A DE 102004015862 A DE102004015862 A DE 102004015862A DE 102004015862 A1 DE102004015862 A1 DE 102004015862A1
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Germany
Prior art keywords
deposition
forming
backsputter
barrier layer
short
Prior art date
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Granted
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DE102004015862A
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English (en)
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DE102004015862B4 (de
Inventor
Michael Friedemann
Volker Kahlert
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to DE102004015862A priority Critical patent/DE102004015862B4/de
Priority to US11/039,103 priority patent/US7071096B2/en
Publication of DE102004015862A1 publication Critical patent/DE102004015862A1/de
Application granted granted Critical
Publication of DE102004015862B4 publication Critical patent/DE102004015862B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Beim Herstellen einer dünnen leitenden Schicht in einer Verbindungsstruktur mittels Sputter-Abscheidung einschließlich eines Rücksputterschrittes wird ein Kurzzeitabscheideschritt nach dem Rücksputterschritt ausgeführt, um eine ausreichende Schichtdicke an kritischen Stellen, etwa an Stellen mit Strukturunregelmäßigkeiten, zu gewährleisten. Der Kurzzeitabscheideschritt kann für eine festgelegte Prozesszeit ausgeführt werden, so dass ein geringer Aufwand bei der Prozesssteuerung erforderlich ist, während gleichzeitig eine erhöhte Zuverlässigkeit im Vergleich zu konventionellen Vorgehensweisen ohne eine Kurzzeitabscheidung erreicht wird.
DE102004015862A 2004-03-31 2004-03-31 Verfahren zur Herstellung einer leitenden Barrierenschicht in kritischen Öffnungen mittels eines abschließenden Abscheideschritts nach einer Rück-Sputter-Abscheidung Expired - Fee Related DE102004015862B4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE102004015862A DE102004015862B4 (de) 2004-03-31 2004-03-31 Verfahren zur Herstellung einer leitenden Barrierenschicht in kritischen Öffnungen mittels eines abschließenden Abscheideschritts nach einer Rück-Sputter-Abscheidung
US11/039,103 US7071096B2 (en) 2004-03-31 2005-01-20 Method of forming a conductive barrier layer within critical openings by a final deposition step after a re-sputter deposition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004015862A DE102004015862B4 (de) 2004-03-31 2004-03-31 Verfahren zur Herstellung einer leitenden Barrierenschicht in kritischen Öffnungen mittels eines abschließenden Abscheideschritts nach einer Rück-Sputter-Abscheidung

Publications (2)

Publication Number Publication Date
DE102004015862A1 true DE102004015862A1 (de) 2005-10-20
DE102004015862B4 DE102004015862B4 (de) 2006-11-16

Family

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DE102004015862A Expired - Fee Related DE102004015862B4 (de) 2004-03-31 2004-03-31 Verfahren zur Herstellung einer leitenden Barrierenschicht in kritischen Öffnungen mittels eines abschließenden Abscheideschritts nach einer Rück-Sputter-Abscheidung

Country Status (2)

Country Link
US (1) US7071096B2 (de)
DE (1) DE102004015862B4 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235860A (ja) 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7256121B2 (en) * 2004-12-02 2007-08-14 Texas Instruments Incorporated Contact resistance reduction by new barrier stack process
JP4728153B2 (ja) * 2006-03-20 2011-07-20 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4812512B2 (ja) * 2006-05-19 2011-11-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
DE102007025341B4 (de) * 2007-05-31 2010-11-11 Advanced Micro Devices, Inc., Sunnyvale Verfahren und Abscheidesystem mit Mehrschrittabscheidesteuerung
US8252690B2 (en) * 2008-02-14 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. In situ Cu seed layer formation for improving sidewall coverage
JP6438831B2 (ja) * 2015-04-20 2018-12-19 東京エレクトロン株式会社 有機膜をエッチングする方法
US10566232B2 (en) 2017-05-18 2020-02-18 Taiwan Semiconductor Manufacturing Co., Ltd. Post-etch treatment of an electrically conductive feature
US10381307B1 (en) * 2018-05-14 2019-08-13 Nanya Technology Corporation Method of forming barrier layer over via, and via structure formed thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735577A2 (de) * 1994-12-14 1996-10-02 Applied Materials, Inc. Abscheidungsverfahren und Einrichtung dafür
WO2002091461A2 (en) * 2001-05-04 2002-11-14 Tokyo Electron Limited Ionized pvd with sequential deposition and etching
US6492262B2 (en) * 1999-01-14 2002-12-10 International Business Machines Corporation Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies

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Publication number Priority date Publication date Assignee Title
US6306732B1 (en) * 1998-10-09 2001-10-23 Advanced Micro Devices, Inc. Method and apparatus for simultaneously improving the electromigration reliability and resistance of damascene vias using a controlled diffusivity barrier
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6764940B1 (en) * 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US6942262B2 (en) 2001-09-27 2005-09-13 Shape Corporation Tubular energy management system for absorbing impact energy
US20030203615A1 (en) * 2002-04-25 2003-10-30 Denning Dean J. Method for depositing barrier layers in an opening
DE10261466B4 (de) * 2002-12-31 2007-01-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer leitenden Barrierenschicht mit verbesserten Haft- und Widerstandseigenschaften
DE10351005B4 (de) * 2003-10-31 2008-07-03 Advanced Micro Devices, Inc., Sunnyvale Barrierenschicht mit einer Titannitridbeschichtung für eine Kupfermetallisierungsschicht, die ein Dielektrikum mit kleinem ε aufweist

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735577A2 (de) * 1994-12-14 1996-10-02 Applied Materials, Inc. Abscheidungsverfahren und Einrichtung dafür
US6492262B2 (en) * 1999-01-14 2002-12-10 International Business Machines Corporation Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies
WO2002091461A2 (en) * 2001-05-04 2002-11-14 Tokyo Electron Limited Ionized pvd with sequential deposition and etching

Also Published As

Publication number Publication date
DE102004015862B4 (de) 2006-11-16
US7071096B2 (en) 2006-07-04
US20050233582A1 (en) 2005-10-20

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OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20131001