DE10196310T1 - Vorrichtung und Verfahren zum Verifizieren eines Chip-Designs und zum Testen eines Chips - Google Patents

Vorrichtung und Verfahren zum Verifizieren eines Chip-Designs und zum Testen eines Chips

Info

Publication number
DE10196310T1
DE10196310T1 DE10196310T DE10196310T DE10196310T1 DE 10196310 T1 DE10196310 T1 DE 10196310T1 DE 10196310 T DE10196310 T DE 10196310T DE 10196310 T DE10196310 T DE 10196310T DE 10196310 T1 DE10196310 T1 DE 10196310T1
Authority
DE
Germany
Prior art keywords
chip
verifying
testing
design
chip design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10196310T
Other languages
English (en)
Other versions
DE10196310B4 (de
DE10196310B8 (de
Inventor
Hyun-Ju Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Park Hyun-Ju Seoul/soul Kr
Yun Dong-Goo Seoul Kr
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of DE10196310T1 publication Critical patent/DE10196310T1/de
Publication of DE10196310B4 publication Critical patent/DE10196310B4/de
Application granted granted Critical
Publication of DE10196310B8 publication Critical patent/DE10196310B8/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
DE10196310T 2000-06-03 2001-06-01 Vorrichtung und Verfahren zum Verifizieren eines Chip-Designs und zum Testen eines Chips Expired - Fee Related DE10196310B8 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
KR2000/30620 2000-06-03
KR20000030620 2000-06-03
KR2000/42575 2000-07-25
KR10-2000-0042575A KR100374328B1 (ko) 2000-06-03 2000-07-25 칩 설계 검증 및 테스트 장치 및 방법
PCT/KR2001/000937 WO2001095238A2 (en) 2000-06-03 2001-06-01 Chip design verifying and chip testing apparatus and method

Publications (3)

Publication Number Publication Date
DE10196310T1 true DE10196310T1 (de) 2003-05-08
DE10196310B4 DE10196310B4 (de) 2009-07-09
DE10196310B8 DE10196310B8 (de) 2009-10-15

Family

ID=26638066

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10196310T Expired - Fee Related DE10196310B8 (de) 2000-06-03 2001-06-01 Vorrichtung und Verfahren zum Verifizieren eines Chip-Designs und zum Testen eines Chips

Country Status (5)

Country Link
US (2) US7185295B2 (de)
JP (1) JP2003536083A (de)
KR (1) KR100374328B1 (de)
DE (1) DE10196310B8 (de)
WO (1) WO2001095238A2 (de)

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JP2012068814A (ja) * 2010-09-22 2012-04-05 Toshiba Corp 半導体記憶装置およびメモリ制御装置
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US8578309B2 (en) * 2012-01-31 2013-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Format conversion from value change dump (VCD) to universal verification methodology (UVM)
US9087613B2 (en) * 2012-02-29 2015-07-21 Samsung Electronics Co., Ltd. Device and method for repairing memory cell and memory system including the device
US9953725B2 (en) * 2012-02-29 2018-04-24 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of operating the same
US8645897B1 (en) * 2013-01-07 2014-02-04 Freescale Semiconductor, Inc. Integrated circuit design verification system
US8739090B1 (en) * 2013-03-15 2014-05-27 Cadence Design Systems, Inc. Probe signal compression method and apparatus for hardware based verification platforms
US10078717B1 (en) 2013-12-05 2018-09-18 The Mathworks, Inc. Systems and methods for estimating performance characteristics of hardware implementations of executable models
US9817931B1 (en) 2013-12-05 2017-11-14 The Mathworks, Inc. Systems and methods for generating optimized hardware descriptions for models
US9659137B2 (en) * 2014-02-18 2017-05-23 Samsung Electronics Co., Ltd. Method of verifying layout of mask ROM
WO2015181759A1 (en) * 2014-05-30 2015-12-03 Insiava (Pty) Ltd. On-chip optical indicator of the state of the integrated circuit
US9893817B2 (en) 2014-05-30 2018-02-13 Insiava (Pty) Ltd. Programmable integrated circuit (IC) containing an integrated optical transducer for programming the IC, and a related IC programming system and method
CN104637546A (zh) * 2015-02-16 2015-05-20 吴中经济技术开发区越溪斯特拉机械厂 内存条卡槽试装机
US9792402B1 (en) * 2015-06-30 2017-10-17 Cadence Design Systems, Inc. Method and system for debugging a system on chip under test
US10423733B1 (en) 2015-12-03 2019-09-24 The Mathworks, Inc. Systems and methods for sharing resources having different data types
US10698805B1 (en) 2017-01-25 2020-06-30 Cadence Design Systems, Inc. Method and system for profiling performance of a system on chip
KR20200052749A (ko) 2018-11-07 2020-05-15 안천수 플래시 스토리지 검증 장치, 방법 및 시스템
CN111989580B (zh) * 2019-01-22 2023-06-30 爱德万测试公司 用于测试一个或多个被测器件的自动化测试设备，用于一个或多个被测器件的自动化测试的方法以及用于应对命令差错的计算机程序
CN111104276B (zh) * 2020-01-02 2024-01-26 小华半导体有限公司 一种芯片测试系统及方法
CN112100954A (zh) * 2020-08-31 2020-12-18 北京百度网讯科技有限公司 验证芯片的方法、装置和计算机存储介质
KR102380506B1 (ko) * 2020-10-29 2022-03-31 포스필 주식회사 전자기기 자가 진단 장치
CN113391970B (zh) * 2021-07-08 2024-03-22 无锡江南计算技术研究所 一种面向异构众核处理器的芯片测试方法及装置
WO2023097298A1 (en) * 2021-11-23 2023-06-01 University Of South Florida Electronic component authenticity identification system and related methods
CN116594830B (zh) * 2023-03-17 2024-03-01 芯华章科技(北京)有限公司 硬件仿真工具、调试方法和存储介质
CN117632621A (zh) * 2024-01-26 2024-03-01 深圳中微电科技有限公司 基于多fpga验证平台的可复用接口配置方法及装置

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Also Published As

Publication number Publication date
KR20010110048A (ko) 2001-12-12
WO2001095238A3 (en) 2002-08-08
KR100374328B1 (ko) 2003-03-03
DE10196310B4 (de) 2009-07-09
WO2001095238A2 (en) 2001-12-13
US7571400B2 (en) 2009-08-04
US20070113209A1 (en) 2007-05-17
US20040138845A1 (en) 2004-07-15
US7185295B2 (en) 2007-02-27
DE10196310B8 (de) 2009-10-15
JP2003536083A (ja) 2003-12-02

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