DE10196179T1 - Verbesserte Abgleichtechnik für Speichervorrichtungen - Google Patents

Verbesserte Abgleichtechnik für Speichervorrichtungen

Info

Publication number
DE10196179T1
DE10196179T1 DE10196179T DE10196179T DE10196179T1 DE 10196179 T1 DE10196179 T1 DE 10196179T1 DE 10196179 T DE10196179 T DE 10196179T DE 10196179 T DE10196179 T DE 10196179T DE 10196179 T1 DE10196179 T1 DE 10196179T1
Authority
DE
Germany
Prior art keywords
storage devices
improved alignment
alignment technology
technology
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10196179T
Other languages
English (en)
Inventor
Brian Johnson
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE10196179T1 publication Critical patent/DE10196179T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072Circuits for initialization, powering up or down, clearing memory or presetting
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
DE10196179T 2000-05-12 2001-05-14 Verbesserte Abgleichtechnik für Speichervorrichtungen Withdrawn DE10196179T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/570,481 US6434081B1 (en) 2000-05-12 2000-05-12 Calibration technique for memory devices
PCT/US2001/015459 WO2001088923A1 (en) 2000-05-12 2001-05-14 Improved calibration technique for memory devices

Publications (1)

Publication Number Publication Date
DE10196179T1 true DE10196179T1 (de) 2003-04-17

Family

ID=24279810

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10196179T Withdrawn DE10196179T1 (de) 2000-05-12 2001-05-14 Verbesserte Abgleichtechnik für Speichervorrichtungen

Country Status (7)

Country Link
US (1) US6434081B1 (de)
JP (1) JP2004516591A (de)
KR (1) KR100564981B1 (de)
AU (1) AU2001261537A1 (de)
DE (1) DE10196179T1 (de)
TW (1) TW514928B (de)
WO (1) WO2001088923A1 (de)

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Also Published As

Publication number Publication date
TW514928B (en) 2002-12-21
WO2001088923A1 (en) 2001-11-22
KR20030013410A (ko) 2003-02-14
US6434081B1 (en) 2002-08-13
JP2004516591A (ja) 2004-06-03
AU2001261537A1 (en) 2001-11-26
KR100564981B1 (ko) 2006-03-28

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R016 Response to examination communication
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee