CS245891B1 - Self-testing logical circuit for checking of one code from twelve - Google Patents

Abstract

The circuit is part of the Computing Department and solves the self-testable 1-in-12 code checking logic. The essence of the circuit is that it has a structural logic scheme consisting of 4 logical levels, the first two logical levels being sum logic members, the third level consists of product members and the fourth level consists of sum logic members. 17 logical members are needed to implement the structural scheme and the total number of inputs of these logical members is 48. Self-testable code checker 1 of 12 will find wide application in the construction of computer parts, such as: bus, interrupt system control, sequential automata. fault detection, inter-code converters, data transfer between computer parts, etc.

Description

245891

BACKGROUND OF THE INVENTION The present invention relates to a self-testable code checking circuit 1 of 12 having 17 logic members with 48 input-ml and four logic levels.

Previously known self-testable code checking circuits 1 of 12 solutions follow. In the first row, this is a solution using a self-testable transcoding control circuit 3 of 6. At the input of this circuit, a logic circuit must be connected - a code conversion transformer 1 of 12 to code 3 of 6.Number of inputs of all logical members of the respective The circuit is 74. Furthermore, it is a solution with cascading the schemes of known solutions. In this case, two parallel operating code-checking circuits are used for checking the code1 of 4. This solution is more cost-effective than the previous solution. For code 1 of 12, the number of inputlogical members of the self-testable code checker 1 is based on 12 according to the 68th. The number of logical levels is 6.

The disadvantages of these two solutions are as follows.

The cost of the solution in the first case quantified by the inputs of all logical members needed to implement the respective structural scheme is 74 inputs. The solution in the second case needs 68 logical member inputs. The number of logical members of the solution is 30. The number of logical levels is 6. Due to the large number of logical levels, the delay in both solutions is large. The unevenness of the structure results in the delays of both output variables being rhizomes.

The above drawbacks are eliminated by the self-printable code checker circuit 1 of 12 consisting of 17 logic members with 48 inputs and 4 logic levels, in accordance with the invention in which the first input terminal is connected to a second input of the fourth sum logic the n and n, and the first input of the second summary member, the second input terminal is connected to the first input of the first summary member and the second input of the seventh bill logical member, the third input is connected to the first input of the fifth bill member and the first input sum logical member, the fourth output terminal is connected to the second input of the second sum logic member and the second input of the eighth sum logic member, the fifth input terminal is connected to the second input of the first sum logic circuit and the first input of the sixth sum logic circuit, siesta entrance fee sv the orc is connected to the third input of the third sum logic circuit and to the second input of the eight sum logic member, the seven input terminal is connected to the second input of the third sum logic circuit, the third input of the eighth sum logic member, the eight input terminal is connected to the fourth input of the second total logic member and to the second input of the sixth bill logical member, the ninth input is connected to the third input of the first billing logic and to the third input I / O logic, the de-wired input terminal is connected to the third input of the third sum logic the third input of the fourth sum logic circuit, the eleventh input terminal is connected to the third input of the second sum logic circuit and to the third input of the nine-log logic circuit, and the two-input terminal is connected to the fourth input of the first sum sum 1 of the fifth sum logical member, the output of the first sum logic member being connected to the first input of the fourth sum logical member and the first digit of the ninth sum logical member, the second member of which is connected to the second input of the fifth sum logic member member and the first input of the seventh sum logical member, the output of the third sum logical member being connected to the third input of the sixth sum member and to the first input of the eighth sum logic member, the sum logical member is connected to a first input of a first product logical member and a second input of a fifth associated logical member, wherein the output of the fifth sum logical member is connected to a first input of a second product logical member; to the second input of the sixth is-act logic member; the output of the sixth total logical member is connected to the first input of the third co-operative member and the second input of the fourth coefficient logical member, the output of the seventh sum logic member being connected to the first input of the fourth co-operative member and the second input of the first coefficient logical member, the logical member is connected to the first input of the fifth co-operative member and to the second input of the second co-operative logical member, the output of the ninth additive logical member being connected to the first input of the sixth co-logical member and the second input of the third co-logic member the product logic member, wherein the outputs of the first product logic member, the second product logic member, and the third product logic member are connected to the entries of the tenth sum member, the output of which is appended to the first output member the output of the fourth product logic member, the fifth-function logic member and the sixth-function logic member, are connected by inputs of an eleventh sum logic member whose output is connected to the second output terminal.

The self-testable logic circuit for code control 1 of 12 according to the invention is advantageous to the previously known similar device because it only requires 48 input logical members of the respective structural script and requires only 17 logical members to re-realize the logical schematic. . it consists of four logical levels of logical schema. As a consequence, substantially lower costs are needed for realization, than the more sophisticated solutions. The failure of both output functions is approximately equal to that because the connection has a regular structure, N, and connected! Figure 1 shows a structure of a self-testable code check circuit 1 of 12. This device pre-stays the implementation of a structural logical schema that is constituted by members of the logic-sum total 11, 12, 13, 21, 22, 23, 24, 25, 26, 41, 42 a, logical product 31 to 36.

The schematic consists of 4 logical levels. I, II, III, IV. The logical summation members 11,12, 13 each have four inputs and one output. The logical sum of 21 to 26, 41, 42, m, and u, three inputs and one output. Logical Level I includes members of logical sum 11,12, 13. Inputs of logical sum member 11 are connected to input terminals 2, 5, 9, 12 and is -h, Oi output is connected to input of logical, sum 21, and 26. Logical Member Inputs. the sum of 12 is connected to the input terminals 1, 4, 6, 11 and the output of the logical sum member 22 and 24 is connected.

The inputs of the logical sum member 13 are connected to the input terminals 3, 6, 7, 10, and the output is connected to the input of the logical sum member 23 and 25. To, logical level no. the logic sum of 21 is connected to the Oift. The input is connected to the inputs of the member of the logical product 31 and 35. The inputs of the member of the logical sum 22 are connected to the input terminals 3, 12 and to the output of the logical sum 13. The output is connected to the inputs of the members of the logical product 32a 10. The inputs of the member of the logical sum 23 are connected to the input terminals 5 "8 and the output of the logical sum 14. The output is connected to the inputs of the members, the logical product 33a34. the logic sum 24 is connected to the input terminals 2, 7 and the output of the logical sum 13. The output is connected to the inputs of the members of the logical product 31a 34. The inputs of the logical sum member 25 are connected to the input terminals 4, fl and to the output of the logic sum member 14 The output is connected to the inputs of the members of the logical file 32 and 35. The inputs of the member of the logical sum 26 are connected to the input terminals S, 11a to the output of the logic member. The output is connected to the inputs of the members of the logical product 33 and 36. The logical level No. III includes the members of the logical product 31 to 36. The inputs of the member of the logical product 31 are connected to the outputs of the member of the logical sum21. and 24. Output to member input, logical sum 41. Inputs Boolean, logical product 32 are connected to outputs of logical sum 22. and 25, output, to a member input, logical connection 41. The input of the logical member member 33 is connected to the outputs of the member of the logical account 23 and 26, the output to the input of the member of logical file 41. of the member of logical sum 42 and the input of logic sum member 21 and 25. The output of np, the input of logical sum 42, the inputs of the logicfunction member 36 are connected to the outputs of the member lo ' The sum of 22 and 26. Output to the logical sum of the input 42. To the logical level. IV includes members of logical sum 41 and 42. Inputs of logical sum member 41 are connected to members' outputs, logical product 3.1,32, 33, and output is connected to output tag 51. Inputs of logical sum member 42 are attached to outputs of logical members 34, 35, 3S and the output is connected n, and output terminal 52, The operation of the self-test code 1 of 12 code checker is as follows. 5.2 will be code 1 of 12. In another code, or in one logical failure, the circuit will output a combination of 0.0 or 1.1, which detects the fault. that, in any logical failure of a logical member, at least one code configuration of code 1 of 12 exists, the error is manifested by the output of the logic member | - F2, i.e. 1.1 or 0.0.

A description of a particular embodiment is given in the explanation of the drawing and, in particular, in the implementation of the logic systems with fault detection, ref. in checking the behavior of a conventional halogen circuit, which works with an internal code 1 of 12. In the case of the circuit of the automatic circuit, or in the self-binding of the circuit, the ones of the internal state and the self-testable logic circuit activate this ppiruohuz. With a small addition, the scheme can also be used for code 11 of 12.

A particular embodiment of the device according to the invention can be used: in designing parts of computer systems that work reliably and safely, such as: code converters from some code to code 1 of 12, re-registers, counters, safe , and reliable control of the selection of one of the twelve units connected to a twelve-line bus, data transmission control, which is encoded with a 1 in 12 code, fail safe design, etc.

Claims (1)

A 1-to-12 code control check logic circuit consisting of 17 logic elements with 48 inputs and four logic levels, characterized in that the first input terminal (11j is connected to the second input of the fourth sum logical element (21) and to the first input of the second sum total) the second input terminal (2) is connected to the first input of the first sum logic element (11) and to the second input of the seventh total logic element (24), the third input terminal (3) is connected to the first input of the fifth total the first input terminal (4) is connected to the second input of the second sum logical member (12) and to the second input of the eighth sum logical member (25), the fifth input terminal (5) is connected to the second input of the first total logic circuit (11) and to the first input of the sixth total logic circuit (23), the sixth input terminal (6) is connected to the third input of the third summation logic circuit (13) to the second input d, of the third summation logic element (26), the seventh input terminal (7) is connected, to the second input of the third summation A logic circuit (13) and a third input of a seventh sum logic element (24), an eight input terminal (8) is connected to a fourth input of the second sum logic element (12) and a second input of a sixth sum logical element (23), ninth, the input terminal (9) is connected to the third input of the first sum logic circuit (11) and to the third input of the seventh sum logic circuit (25), the tenth input terminal (10) is connected to the fourth input of the third sum logic circuit! the third input terminal (11) is connected to the third input of the second total logic circuit (12) and to the third input of the ninth total logic circuit (26) and the twelfth input circuit. the terminal (12) is connected to the fourth input of the first sum logical member (11) and to the third input of the fifth sum logical member (22), the output of the first sum logical member (11) being connected to the first input of the fourth logical member (21) and the first input of the ninth summation logic OF THE INVENTION (26), wherein the output of the second sum logical member (12) is connected to the second input of the fifth sum logical member (22) and to the first input of the seventh sum logical member (24), the output of the third sum logical member (13) connected a third input of the sixth sum logical member (23) and a first input of the eighth sum logical member (25), the output of the fourth sum logical member (21) being connected to a first input of the first product logical member (31) and a second input of the fifth product A logic member (35), wherein the output of the fifth total logical member (22) is connected to the first input of the second product logical member (32) and to the second input of the sixth product logical member (36), the output of the sixth total logical member (23) is connected to the first input of the third product logic element (33) and to the second input of the fourth a product logic member (34), the output of the seventh total logic member (24) being connected to the first input of the fourth product logic member (34), the output of the seventh total logic member (24) being connected to the first input of the fourth product logic member (34) and a second input of the first product logic element (31), the output of the eighth sum logic element (25) being connected to the first input of the fifth product logic element (35) and to the second input of the second, product logic element (32), the output the ninth sum logical member (26) is connected to the first input of the sixth product logical member (36) and to the second input of the third product logical member (33), the outputs of the first product logical member (3.1), the second product logical member (32) and the third product logic member (33) is connected to the inputs of the tenth totals a member (41) whose output is connected to a first output terminal (51), the outputs of a fourth product logic member (34), a fifth product logic member (35), and a sixth product logic member (36) are connected to inputs of an eleventh sum logic member (42), the output of which is connected to a second output terminal (52).