CS219319B2 - Method of executing the instructions for treating the data gradually received in the given signal sequence - Google Patents

Method of executing the instructions for treating the data gradually received in the given signal sequence Download PDF

Info

Publication number
CS219319B2
CS219319B2 CS763237A CS323776A CS219319B2 CS 219319 B2 CS219319 B2 CS 219319B2 CS 763237 A CS763237 A CS 763237A CS 323776 A CS323776 A CS 323776A CS 219319 B2 CS219319 B2 CS 219319B2
Authority
CS
Czechoslovakia
Prior art keywords
instruction
data
gate
type
instructions
Prior art date
Application number
CS763237A
Other languages
Czech (cs)
English (en)
Inventor
Karl-Johan W Carlsson
Erik I Sjoeqist
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of CS219319B2 publication Critical patent/CS219319B2/cs

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
CS763237A 1975-05-14 1976-05-14 Method of executing the instructions for treating the data gradually received in the given signal sequence CS219319B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE7505552A SE7505552L (sv) 1975-05-14 1975-05-14 Sett och anordning att efter varandra avverka databehandlingsinstruktioner i funktionsenheter hos en datamaskin

Publications (1)

Publication Number Publication Date
CS219319B2 true CS219319B2 (en) 1983-03-25

Family

ID=20324577

Family Applications (1)

Application Number Title Priority Date Filing Date
CS763237A CS219319B2 (en) 1975-05-14 1976-05-14 Method of executing the instructions for treating the data gradually received in the given signal sequence

Country Status (27)

Country Link
US (1) US4053947A (fr)
JP (1) JPS5942893B2 (fr)
AR (1) AR212022A1 (fr)
AU (1) AU510011B2 (fr)
BE (1) BE841694A (fr)
BR (1) BR7603014A (fr)
CA (1) CA1068006A (fr)
CH (1) CH613538A5 (fr)
CS (1) CS219319B2 (fr)
DD (1) DD125023A5 (fr)
DE (1) DE2619661A1 (fr)
DK (1) DK214276A (fr)
EG (1) EG13391A (fr)
ES (1) ES447844A1 (fr)
FI (1) FI761315A (fr)
FR (1) FR2311356A1 (fr)
GB (1) GB1529638A (fr)
HU (1) HU182481B (fr)
IN (1) IN156422B (fr)
IT (1) IT1063311B (fr)
MY (1) MY8000079A (fr)
NL (1) NL7604966A (fr)
NO (1) NO761661L (fr)
PL (1) PL116724B1 (fr)
SE (1) SE7505552L (fr)
SU (1) SU755225A3 (fr)
YU (1) YU40281B (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
SE430199B (sv) * 1982-02-12 1983-10-24 Ellemtel Utvecklings Ab Sett och anordning for att ge identitet at och utpeka en av ett antal funktionsenheter
US4511961A (en) * 1982-04-16 1985-04-16 Ncr Corporation Apparatus for measuring program execution
US4656580A (en) * 1982-06-11 1987-04-07 International Business Machines Corporation Logic simulation machine
JPH0217808Y2 (fr) * 1984-10-29 1990-05-18
JPS6250085U (fr) * 1985-09-14 1987-03-27
US6904480B1 (en) * 1997-12-17 2005-06-07 Intel Corporation Testing a bus using bus specific instructions
US8914615B2 (en) 2011-12-02 2014-12-16 Arm Limited Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3215987A (en) * 1962-06-04 1965-11-02 Sylvania Electric Prod Electronic data processing
US3657705A (en) * 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding
JPS514381B1 (fr) * 1969-11-24 1976-02-10
US3766532A (en) * 1972-04-28 1973-10-16 Nanodata Corp Data processing system having two levels of program control

Also Published As

Publication number Publication date
ES447844A1 (es) 1977-07-16
JPS5942893B2 (ja) 1984-10-18
FR2311356A1 (fr) 1976-12-10
FI761315A (fr) 1976-11-15
HU182481B (en) 1984-01-30
JPS51140451A (en) 1976-12-03
CA1068006A (fr) 1979-12-11
AR212022A1 (es) 1978-04-28
DK214276A (da) 1976-11-15
NO761661L (fr) 1976-11-16
BR7603014A (pt) 1977-01-11
CH613538A5 (fr) 1979-09-28
YU116976A (en) 1982-06-30
BE841694A (fr) 1976-09-01
DE2619661A1 (de) 1976-12-02
AU510011B2 (en) 1980-06-05
AU1387576A (en) 1977-11-17
PL116724B1 (en) 1981-06-30
GB1529638A (en) 1978-10-25
SE7505552L (sv) 1976-11-15
YU40281B (en) 1985-12-31
IT1063311B (it) 1985-02-11
US4053947A (en) 1977-10-11
NL7604966A (nl) 1976-11-16
MY8000079A (en) 1980-12-31
SU755225A3 (en) 1980-08-07
FR2311356B1 (fr) 1980-07-11
EG13391A (en) 1981-03-31
IN156422B (fr) 1985-07-27
DD125023A5 (fr) 1977-03-23

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