CN87106380A - 外引线带的自动焊接法 - Google Patents

外引线带的自动焊接法 Download PDF

Info

Publication number
CN87106380A
CN87106380A CN198787106380A CN87106380A CN87106380A CN 87106380 A CN87106380 A CN 87106380A CN 198787106380 A CN198787106380 A CN 198787106380A CN 87106380 A CN87106380 A CN 87106380A CN 87106380 A CN87106380 A CN 87106380A
Authority
CN
China
Prior art keywords
lead
band
substrate
chip
outer race
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN198787106380A
Other languages
English (en)
Inventor
戴维·L·哈洛韦尔
约翰·W·索菲亚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of CN87106380A publication Critical patent/CN87106380A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10424—Frame holders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Cable Accessories (AREA)
  • Controlling Rewinding, Feeding, Winding, Or Abnormalities Of Webs (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

公开了将带与芯片组成的部件导电触指的外引线与封装衬底对齐并焊接的一种方法。各带段都设有一个内座圈和一个外座圈。导电指从内座圈底下延伸到外座圈底下。外座圈距内座圈一段距离，以暴露其间的带外引线部分。带与芯片组成的部件安置在封装衬底上面，使外引线与适当的封装衬底引线对齐。在衬底与外座圈之间的至少一个位置上涂以焊剂沉积物将部件焊接到衬底上。焊接好的外座圈避免部件移动，因而不致使引线在焊接之前和焊接过程中与衬底不对齐。

Description

本发明是关于将集成电路芯片焊接到衬底上的一种新方法，更详细地说，是关于将带的外引线和集成电路芯片部件焊接到衬底上的一种新方法。
封装是制造集成电路元件工艺中的一个工序。封装时，将制好的半导体芯片装进一个保护封装中。装配好的元件经过测试然后连接到专为其设计的电子电路上。封装配备有外部引线，使元件可藉这些引线连接到电子电路上。
封装过程中的一个难点在于芯片与封装外部引线的连接，必须小心谨慎确保芯片上各焊接点或连接点妥善连接到适当的外部引线上。如果不能全部正确无误地进行接线则会使元件误动作或不动作。
目前连接芯片与封装引线的方法是采用带的自动焊接法（TAB）。TAB法采用具有多个专用带段的聚酰亚胺薄膜带。各段包括界定着一中心小孔的薄膜座圈。座圈底下用腐蚀法形成多个导电指。各导电指具有一个延伸入中心小孔的内引线和超出座圈周边延伸的外引线。芯片安置在小孔上，使芯片上各焊接点与适当的内引线对齐。然后将焊接点焊接到内引线上。
接着将带与芯片引线组成的部件从带上切去，将其安置在封装衬底上，使各引线与连接到封装外部引线的适当的封装衬底引线对齐。外引线经与衬底引线的焊接就将芯片连接到适当的封装外引线上。
有关带的自动焊接工艺更详细的讨论见Sze在《超大规模集成电路技术》（1983年）第559～564页编写的文章和Dais，Erich和Jaffe在电气与电子工程师协会元器件、混合电路和制造技术会报（1980年12月）第623～633页写的“混合电路用的倒装的TAB”一文中，这两篇文章也包括在本说明书中以供参考。
带的自动焊接法是将半导体芯片连接到封装上的有效方法。各带段可在带上配置得使芯片可自动焊接到带上。通过对带进行适当的刻蚀就可使各芯片的导电指密集地封装在带段上。这是超大规模集成芯片制造工艺中一个极其重要的特点，其中每一个芯片上往往有100到300以上的焊接点。
但实践证明，要将密集封装好的带外引线与封装衬底各引线对齐并焊接起来是有困难的。这有三个原因：（1）引线中的卷曲力沿带的轴向与线两端轴线上的不同;（2）金属导电指和薄膜（其上金属导电指被腐蚀）的卷曲是不同的，这促使部件的各引线卷曲;最后，（3）当将热焊接片往下压在各外引线上时，各个外引线产生横向/纵向滑动。此卷曲和滑动动作使各个外引线在衬底焊接之前很难保证对齐。
外引线的卷曲和滑动还给引线焊接之前对带与芯片组装情况的检查带来困难。为避免外引线因卷曲而对不齐，需要将外部引线迅速焊接到衬底引线上。必须在以后的检查和再焊接工序中较正任何存在的错误，例如细微的不对齐情况等。
当每个部件中的外引线为10～100个，且各引线间距大于0.012英寸时，这些问题较易于纠正。但各超大规模集成部件的引线会多达100或以上。诸外引线系密集地封装在一起，即各引线之间的间距非常小。因此要将超大规模集成TAB部件的带外引线与封装衬底引线对齐并焊接起来极其困难。这历来是高效制造超大规横集成元件的主要障碍。
因此需要有一种将带与芯片组成的部件各导电指引线的外引线焊接到适当的衬底引线的新方法。新方法应在任何引线密度下都能使大量外引线端部与适当的衬底引线妥善对齐。新方法还应能防止外引线在压焊接到衬底引线之前卷曲。此外，新方法应便于对部件在其在衬底上对齐之后作为中间工序进行检查。这样就可以在将带引线焊接到衬底之前校正没有对齐的引线。新的焊接方法还应能在为将带外引线焊接到衬底引线而施加压焊工具时防止外引线滑动。
根据本发明，各带段外引线端部都配有薄膜外座圈。各带与芯片组成的部件都有一圈内引线、一内座圈、一圈外露的外引线和一外座圈，粘结到外引线端部的尖端。外座圈起防止外部引线端部在粘结到衬底之前卷曲的作用。
衬底是为部件而制备的，方法是先将粘稠性的热焊剂沉积物涂在封装衬底的焊接区上。衬底应加热得使焊剂仍具粘性。将带与芯片组成的部件安置在焊接区上，使其与焊剂沉积物接触，且使带外引线与适当的封装衬底引线对齐。其次冷却衬底使焊剂固化。固化的焊剂使带的外座圈与衬底结合在一起，并使带的外引线与衬底引线对齐。
这个工序使带外引线较易以焊接到衬底引线上。在这方面，外座圈起两个作用。首先，外座圈起约束外引线的作用，特别是防止它们卷曲。其次，外座圈在焊接到衬底上之后起固定外引线的作用，使其与衬底引线对齐。这提供了在焊接之前彻底检查各引线的中间机会，因为这时外引线卷曲或与衬底引线不对齐的可能性不大。万一检测出任何差错，还有机会在焊接之前予以纠正。由于各引线活动的余地受到限制，要用微小工具纠正出现的任何差错就比较容易了。
外座圈还在施加焊接工具以将引线焊接到衬底引线上时起防止外引线离位滑动的作用。
上述工艺特别适用于超大规模集成元件的制造。
图1是现有技术带与芯片组成的部件的平面图。
图2是本发明最佳实施例一个在封装衬底上对齐了的带与芯片部件的等角视图。
图3是本发明最佳实施例引线带的剖视图。
图4是本发明最佳实施例的一个带与芯片组成的部件在封装衬底上对准过程情况的组件分解等角示意图。
图5是图2带与芯片组成的部件一角的放大平面图。
图6是沿图5中6-6线截取的带与芯片组成的部件的横向剖视图。
图1是现有技术带与芯片组成的部件100的示意图。芯片102焊接到带部分104上。带部分包括单个座圈106，座圈106底面刻蚀有多个导电指108。各导电指有一个延伸出座圈外周边的外引线110和在底面焊接到芯片102的内引线（图中未示出）。外引线没有受约束，在处理过程中各个引线会卷曲或交叉，分别如112和114处所示。因此需要迅速将各引线焊接到衬底上面无需首先检查有无开路、短路或不对齐的引线。此外使用焊接工具将外引线连接到衬底引线上时不能防止个别外引线滑动离位。
图2是本发明带与芯片组成的部件10焊接到封装衬底12上的示意图。部件10包括焊接引线带14切除部分的半导体芯片13。引线带14底下刻蚀有多个导电指16。芯片10和衬底12之间必须加以延伸的电气连接是供借助于足量的导电指进行的。更具体地说，各导电指围绕半导体芯片延伸出方形聚酰亚胺内座圈18。各导电指末端设有外引线20。外引出线端部有一个方形外座圈22，也是聚酰亚胺薄膜制成的。外座圈内周边与内座圈外周边相隔一段距离，使外引线的部分23暴露在该两周边之间着。
带与芯片组成的部件10安置在衬底安装区24上。衬底引线26埋置在衬底安装区24上，与封装外部引线（图中未示出）相连。部件安置在衬底上，使各个外引线部分覆在适当的衬底引线上。带和芯片组成的部件在外座圈22的各拐角30用焊剂28的沉积物固定到衬底上。
从图3可以清楚地看到，本工艺所用的带32包含多个逐次配置的带段34。各带段底下刻蚀有多个导电指16。内座圈13和外座圈22都是刻蚀形成的，以便使带引线部分23暴露在内外座圈之间。中心小孔36是从内座圈刻蚀的，以便暴露从各导电指延伸的下带引线38。各导电指在内座圈18和外座圈22底下延伸，在毗邻带段外周边的测试区40处终止。带的两边42设有导孔44。
按标准TAB安装操作法将半导体芯片13装在各带段34的中心小孔36。导孔是为使带能通过TAB芯片焊接机（图中未示出）向前推进而设的。在芯片焊接的过程中，内引线连接到芯片上适当的焊接点上。测试区40便于在焊接之后测试带与芯片连接情况之用。经过焊接和测试之后，将带与芯片组成的部件10沿外座圈22的外边缘从带32上切除。
往衬底上焊接带与芯片组成的部件10的第一步工序是将焊剂沉积物28涂到衬底上，如图4所示。焊剂系涂到衬底上外座圈22拟与衬底连接且外引线20与衬底26不焊接在一起的部位。例如，这可以是外座圈拐角部分30处在衬底上的部位，如图5所示。较理想的焊剂为树脂膏焊剂，焊剂中的溶剂（例如丁基卡必和苄醇）已蒸发掉。这样得出的焊剂在100℃以下变硬，在120℃至150℃范围内变粘。焊剂是在大约125℃温度下涂到衬底上。往衬底上涂焊剂可采用自动“跳销（pogo    pin）/储槽”式装置（图中未示出）。衬底保持加热在约125℃的温度，以确保它保持粘性但不致流过衬底。
然后将带与芯片组成的部件10放到衬底12上。采用TAB装配技术令部件10就位，使外引线20与适当的衬底引线26对齐。部件10妥善对齐之后，令衬底冷却下来，使焊剂28固化，从而将外座圈22固定到衬底的适当位置上。外圈又使各带外引线20就位，如图6所示。
将带与芯片部件10用焊剂焊接到衬底12之后，就可检查外引线20。由于外引线都受约束不动，因而可以全面检查焊接好各组件的孔口、有无短路和细微的不对齐现象等。任何缺陷都可用热探针修理。组件经检查，必要时修理之后，就可用标准的微焊接技术将带外引线焊接到衬底引线上。在焊接外引线的过程中，在使用焊接工具时，外座圈起防止外部引线滑动的作用。这时就可将组件用于封装过程的最后工序中。
本发明的对齐和焊接法特别适用于制造超大规模集成元件。外座圈能约束任何数量的外引线的运动。用焊剂将带与芯片组成的部件焊接到衬底使外引线在检查和引线焊接过程中保持对齐。这样，即使诸引线系密集地封装在一起，也可以大大减轻将外引线焊接到衬底上所需的劳力。在小空间中制造具有大量引线的超大规模集成元件时，这些特点很重要。

Claims (13)

1、将引线带与芯片组成的部件焊接到封装衬底上的一种方法，引线带具有多个电气连接到芯片上的导电指，各导电指具有一个安置在芯片末端的外引线，该引线是要焊接到封装衬底上特定的衬底引线上的，该方法的特征在于，该方法包括下列步骤：
甲.带与芯片组成的部件设有一个带外座圈部分，覆盖并附着在带外引线的外端部起约束各外引线使其不动的作用；
乙.将带与半导体芯片部件安置在衬底上，使各带的外引线与适当的封装衬底引线对齐；
丙.将外座圈压焊接到衬底上，以便对对齐了的部件带外引线的运动起约束作用。
2、根据权利要求1的方法，其特征在于，外座圈系焊接到衬底上，方法是在至少一选择部位上在带外圈与衬底之间涂上粘性物质。
3、根据权利要求2的方法，其特征在于，粘性物质是个焊剂，所述焊剂在第一种温度下是硬的，在高于第一种温度的温度下是粘稠的，带外座圈系按下列步骤焊接到衬底上：
甲.往衬底上准备将外座圈安置在衬底上的至少一个位置涂上加热到第二温度的焊剂沉积物;
乙.将所述衬底加热到所述第二温度，使所述焊剂变得粘稠;
丙.将带与芯片组成的部件安置就位，使带的外引线与适当的封装引线对齐，且外座圈安置在焊剂沉积物上;
丁.将所述衬底冷却至所述第一温度，使焊剂固化，从而使带与芯片组成的部件焊接到衬底上。
4、根据权利要求2的方法，其特征在于，所选择的在所述带外座圈与封装衬底之间涂敷所述焊剂的部位没有封装衬底引线和带外引线。
5、根据权利要求4的方法，其特征在于，所述外座圈呈多角形，带外部引线距具有若干个拐角的多角形的各角一段距离，且所述多角形的至少一个拐角安置在焊剂沉积物中。
6、根据权利要求3的方法，其特征在于，所述焊剂是已除去溶剂的树脂膏焊剂。
7、一种将半导体芯片电气连接到封装衬底的的引线带段，该引线带具有多个导电指，用以将半导体芯片上的焊接点连接到封装衬底上的衬底引线，其特征在于，该引线带段包括：
甲.各导电指具有一个内引线和一个外引线，外引线用以焊接到半导体芯片的焊接点，外引线末端距内引线一段距离配置，用以焊接到衬底引线上;
乙.一个内座圈，覆盖在所述导电指上，介于所述内引线和外引线之间，所述座圈具有一个小孔，用以接收半导体芯片，所述内引线延伸入所述中心小孔中;和
丙.一个约束装置，用以约束各个外引线的运动。
8、根据权利要求7的引线带段，其特征在于，所述约束装置包括为所述带提供的一个外座圈，覆盖在该外引线端上，距所述内座圈一段距离。
9、根据权利要求9的带段，其特征在于，所述外座圈上至少有一个没有外部引线的部位。
10、根据权利要求7的带段，其特征在于，多个引线带段结合在一起形成一个带，所述带适宜用自动焊接机将半导体芯片焊接到各带段上。
11、根据权利要求7的引线带段，其特征在于，所述外引线固定装置适宜焊接到封装衬底上。
12、根据权利要求8的引线段，其特征在于，所述外座圈呈多角形，具有多个拐角。
13、根据权利要求12的引线段，其特征在于，所述外引线距所述外座圈的至少一个拐角一段距离。
CN198787106380A 1986-08-27 1987-08-27 外引线带的自动焊接法 Pending CN87106380A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US90078986A 1986-08-27 1986-08-27
US900789 1986-08-27

Publications (1)

Publication Number Publication Date
CN87106380A true CN87106380A (zh) 1988-06-08

Family

ID=25413083

Family Applications (1)

Application Number Title Priority Date Filing Date
CN198787106380A Pending CN87106380A (zh) 1986-08-27 1987-08-27 外引线带的自动焊接法

Country Status (10)

Country Link
EP (1) EP0259222B1 (zh)
JP (1) JPS63114226A (zh)
KR (1) KR880003422A (zh)
CN (1) CN87106380A (zh)
AT (1) ATE87397T1 (zh)
AU (1) AU596443B2 (zh)
BR (1) BR8705103A (zh)
CA (1) CA1281435C (zh)
DE (1) DE3784987T2 (zh)
IN (1) IN171404B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4761880A (en) * 1986-12-08 1988-08-09 International Business Machines Corporation Method of obtaining surface mount component planarity
US5156983A (en) * 1989-10-26 1992-10-20 Digtial Equipment Corporation Method of manufacturing tape automated bonding semiconductor package
US5099392A (en) * 1990-04-02 1992-03-24 Hewlett-Packard Company Tape-automated bonding frame adapter system
GB9018764D0 (en) * 1990-08-28 1990-10-10 Lsi Logic Europ Packaging of electronic devices
GB2257827B (en) * 1991-07-17 1995-05-03 Lsi Logic Europ Support for semiconductor bond wires
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
JPH07101699B2 (ja) * 1993-09-29 1995-11-01 インターナショナル・ビジネス・マシーンズ・コーポレイション 印刷回路基板及び液晶表示装置
US6334765B1 (en) * 1998-10-21 2002-01-01 Engel Maschinenbau Gesellschaft M.B.H. Injection molding machine having a C-form frame
US20210249339A1 (en) * 2020-02-10 2021-08-12 Delta Electronics, Inc. Package structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52156560A (en) * 1976-06-23 1977-12-27 Hitachi Ltd Semiconductor device and its production
EP0016522B1 (en) * 1979-02-19 1982-12-22 Fujitsu Limited Semiconductor device and method for manufacturing the same
US4466183A (en) * 1982-05-03 1984-08-21 National Semiconductor Corporation Integrated circuit packaging process
DE3219055A1 (de) * 1982-05-21 1983-11-24 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Verfahren zur herstellung eines filmtraegers mit leiterstrukturen
US4571354A (en) * 1983-12-27 1986-02-18 Rogers Corporation Tape automated bonding of integrated circuits
DE3512628A1 (de) * 1984-04-11 1985-10-17 Moran, Peter, Cork Packung fuer eine integrierte schaltung
DE3674292D1 (de) * 1985-07-23 1990-10-25 Fairchild Semiconductor Verpackungsanordnung fuer halbleiterchip und verfahren zum erleichtern deren pruefung und montage auf ein substrat.
US4721993A (en) * 1986-01-31 1988-01-26 Olin Corporation Interconnect tape for use in tape automated bonding

Also Published As

Publication number Publication date
DE3784987D1 (de) 1993-04-29
DE3784987T2 (de) 1993-10-14
EP0259222A2 (en) 1988-03-09
JPH0454379B2 (zh) 1992-08-31
EP0259222B1 (en) 1993-03-24
JPS63114226A (ja) 1988-05-19
AU596443B2 (en) 1990-05-03
KR880003422A (ko) 1988-05-17
IN171404B (zh) 1992-10-03
BR8705103A (pt) 1988-04-26
CA1281435C (en) 1991-03-12
AU7743487A (en) 1988-03-03
ATE87397T1 (de) 1993-04-15
EP0259222A3 (en) 1988-09-07

Similar Documents

Publication Publication Date Title
US4466183A (en) Integrated circuit packaging process
US4994411A (en) Process of producing semiconductor device
US6163463A (en) Integrated circuit chip to substrate interconnection
US6222258B1 (en) Semiconductor device and method for producing a semiconductor device
KR100372153B1 (ko) 다층리드프레임
US7042098B2 (en) Bonding pad for a packaged integrated circuit
US4839713A (en) Package structure for semiconductor device
US5559316A (en) Plastic-molded semiconductor device containing a semiconductor pellet mounted on a lead frame
CN87106380A (zh) 外引线带的自动焊接法
US5569956A (en) Interposer connecting leadframe and integrated circuit
JP2002184934A (ja) 半導体装置及びその製造方法
US6032852A (en) Reworkable microelectronic multi-chip module
KR100198682B1 (ko) 반도체 디바이스 제조방법
JPH0677398A (ja) オーバモールド形半導体装置及びその製造方法
JPS59222947A (ja) 半導体装置およびその製造方法
US7015585B2 (en) Packaged integrated circuit having wire bonds and method therefor
US5841188A (en) Tape carrier structure for a tape carrier package
JPH0658924B2 (ja) 半導体デバイスパッケージ及びその製造方法
US6814274B2 (en) Bonding tool capable of bonding inner leads of tab tapes to electrode pads in high quality and high productivity and bonding method
US20080079175A1 (en) Layer for chip contact element
JP2712525B2 (ja) 半導体装置の製造方法
JP2888036B2 (ja) 半導体装置の製造方法
JPH05160215A (ja) 半導体装置用評価装置
JP2699557B2 (ja) Ｔａｂ形式半導体装置の製造方法
JPH11251471A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication