CN2819477Y - 模块卡的堆叠构造 - Google Patents

模块卡的堆叠构造 Download PDF

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CN2819477Y
CN2819477Y CN200520016993.8U CN200520016993U CN2819477Y CN 2819477 Y CN2819477 Y CN 2819477Y CN 200520016993 U CN200520016993 U CN 200520016993U CN 2819477 Y CN2819477 Y CN 2819477Y
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chip
substrate
layer chip
lower floor
glue
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张鸿租
白忠巧
龙港文
林仕祥
黄文亨
龙昌宏
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Kingpak Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body

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Abstract

本实用新型是一种模块卡的堆叠构造，其包括有：一基板，其设有一上表面及一下表面，该上表面形成有多个第一电极；一二次胶，涂布于所述上表面；一下层芯片，设置于所述上表面，位于该二次胶上方；多条导线，电连接该下层芯片至该基板的第一电极；一粘着剂，包括有胶体及填充元件，涂布于该下层芯片上；一上层芯片，通过粘着剂粘设于该下层芯片上，通过该填充元件与下层芯片隔离，且通过该多条导线电连接至该基板的第一电极；及一封胶层，包覆该上、下层芯片及导线。其中所述二次胶是以网印方式涂布于该基板上，所述粘着剂的填充元件为球状。本实用新型可减小产品体积，且制造便利，可降低生产成本及提高信赖度。

Description

模块卡的堆叠构造
技术领域
本实用新型涉及模块卡的堆叠构造，尤其涉及一种可减小产品体积、制造便利，且可降低生产成本及提高信赖度的模块卡的堆叠构造。
背景技术
已知的模块卡堆叠构造，在制造时是利用传统的非导电胶在芯片与芯片及芯片与基板间作结合，由于传统的非导电胶是以点胶方式涂布于该基板与芯片间，因此，该胶量的控制相当不易。因此，常造成下层芯片无法平整地粘着在该基板上，使得上层芯片也无法平整地与下层芯片作结合。
因此，其产品高度因非导电胶的特性，使得封装的制造过程难以控制，而且也可能造成芯片裂损的现象。
有鉴于此，本案设计人本着精益求精、创新突破的精神，致力于影像传感器封装的研发，而设计出本实用新型模块卡的堆叠构造，使其制造上更为便利及提高其信赖度。
实用新型内容
本实用新型的主要目的，在于提供一种模块卡的堆叠构造，其具有减小产品体积的功效，以达到轻薄短小的目的。
本实用新型的另一目的，在于提供一种模块卡的堆叠构造，其具有制造便利的功效，以达到降低生产成本及提高信赖度的目的。
本实用新型模块卡的堆叠构造包括有一基板，其设有一上表面及一下表面，该上表面形成有多个第一电极；一二次(B-Stage)胶，涂布于该基板的上表面；一下层芯片，设置于该基板的上表面，位于该二次胶上方；多条导线，用以电连接该下层芯片至该基板的第一电极；一粘着剂，包括有胶体及填充元件，涂布于该下层芯片上；一上层芯片，通过粘着剂粘设于该下层芯片上，通过该填充元件与下层芯片隔离，且通过该多条导线电连接至该基板的第一电极；及一封胶层，用以包覆该上、下层芯片及导线。
本实用新型模块卡的堆叠构造的制造方法包括下列步骤：提供一基板，其设有一上表面及一下表面，该上表面形成有多个第一电极；提供一二次(B-Stage)胶涂布于该基板的上表面，进行第一次烘烤，使其暂时硬化；提供一下层芯片设置于该基板的上表面，位于该二次胶上方，进行第二次烘烤，使该下层芯片与该基板粘着固定；提供多条导线用以电连接该下层芯片至该基板的第一电极；提供一粘着剂，包括有胶体及填充元件，涂布于该下层芯片上；提供一上层芯片通过粘着剂粘设于该下层芯片上，通过该填充元件与下层芯片隔离，且通过该多条导线电连接至该基板的第一电极；及提供一封胶层用以包覆该上、下层芯片及导线。
本实用新型的有益效果在于：利用网印方式将二次胶平整地涂布基板上，使得下层芯片可平整地固着于基板上，上层芯片通过填充元件堆叠，可防止芯片的倾斜，而避免封胶后芯片外露的现象，可提高产品的信赖度。
附图说明
图1是本实用新型模块卡的堆叠构造的剖视图；
图2是本实用新型模块卡的堆叠构造的制造方法的第一示意图；
图3是本实用新型模块卡的堆叠构造的制造方法的第二示意图；
图4是本实用新型模块卡的堆叠构造的制造方法的第三示意图。
主要元件符号说明：
10：基板      12：二次胶  14：下层芯片
16：多条导线  18：粘着剂  20：上层芯片
22：封胶层    24：上表面  26：下表面
28：第一电极  30：胶体  32：填充元件
具体实施方式
本实用新型的上述及其它目的、优点和特色由以下较佳实施例的详细说明并参考图式得以更深入了解。
请参阅图1，其为本实用新型模块卡的堆叠构造，其包括有一基板10、一二次胶12、一下层芯片14、多条导线16、一粘着剂18、一上层芯片20及一封胶层22，其中：
基板10设有一上表面24及一下表面26，上表面24形成有多个第一电极28；
一二次(B-Stage)胶12以网印方式涂布于基板10的上表面24，进行第一次烘烤，使其暂时硬化，如此，以网印方式涂二次胶时，可平整地将二次胶(B-Stage)12涂布于基板10上；
一下层芯片14设置于基板10的上表面24，位于硬化的二次胶(B-Stage)12上方，进形第二次烘烤，使二次胶(B-Stage)12软化后将下层芯片14粘着固定，如此，即可将下层芯片14平整地固定于基板10上；
多条导线16用以电连接下层芯片14至基板10的第一电极28上；
一粘着剂16包括有胶体30及填充元件32，涂布于下层芯片14上，本实施例中填充元件32为球状；
一上层芯片20通过粘着剂18粘设于下层芯片14上，通过填充元件32与下层芯片14隔离，且由多条导线16电连接至基板10的第一电极28；及
一封胶层22用以包覆上、下层芯片及多条导线16。
请参阅图2，其为本实用新型模块卡的堆叠构造的制造方法的第一示意图，首先提供一基板10，于基板10的上表面24以网印方式涂布一层二次胶(B-Stage)12，再进行第一次烘烤。
请配合参阅图3，其为本实用新型模块卡的堆叠构造的制造方法的第二示意图，提供一下层芯片14，将其设置于基板10的上表面24上，并位于二次胶(B-Stage)12上，进行第二次烘烤，使下层芯片14平整地粘着于基板10上；
提供多条导线16用以电连接下层芯片14至基板10的第一电极28上。
请参阅图4，其为本实用新型模块卡的堆叠构造的制造方法的第三示意图，提供一粘着剂16，其包括有胶体30及填充元件32，涂布于下层芯片14上，本实施例中填充元件32为球状；
提供一上层芯片20通过粘着剂18粘设于下层芯片14上，通过填充元件32与下层芯片14隔离，且由多条导线16电连接至基板10的第一电极28。
最后，如图1所示，提供一封胶层22用以包覆上、下层芯片及多条导线16。
如此，本实用新型利用网印方式将二次胶12平整地涂布基板10上，使得下层芯片14可平整地固着于基板10上，上层芯片20通过填充元件32堆叠，可防止芯片的倾斜，而避免封胶后芯片外露的现象，可提高产品的信赖度。
在较佳实施例的详细说明中所提出的具体实施例仅为了易于说明本实用新型的技术内容，并非将本实用新型狭义地限制于实施例，凡依本实用新型的精神及申请专利范围的情况所作种种变化实施均属本实用新型的范围。

Claims (3)

1.一种模块卡的堆叠构造，其特征在于包括有：
一基板，其设有一上表面及一下表面，该上表面形成有多个第一电极；
一二次胶，涂布于该基板的上表面；
一下层芯片，设置于该基板的上表面，位于该二次胶上方；
多条导线，电连接该下层芯片至该基板的第一电极；
一粘着剂，包括有胶体及填充元件，涂布于该下层芯片上；
一上层芯片，通过粘着剂粘设于该下层芯片上，通过该填充元件与下层芯片隔离，且通过该多条导线电连接至该基板的第一电极；及
一封胶层，包覆该上、下层芯片及导线。
2.如权利要求1所述的模块卡的堆叠构造，其特征在于，所述二次胶是以网印方式涂布于该基板上。
3.如权利要求1所述的模块卡的堆叠构造，其特征在于，所述粘着剂的填充元件为球状。
CN200520016993.8U 2005-04-21 2005-04-21 模块卡的堆叠构造 Expired - Lifetime CN2819477Y (zh)

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