CN219715983U - Liquid crystal display module control system based on high-speed singlechip - Google Patents

Abstract

The utility model relates to the technical field of display screens, in particular to a liquid crystal display module control system based on a high-speed singlechip, which comprises a DSP module, an FPGA module, a storage module, RJ45 interfaces and an LCD display screen, wherein data communication is established between the DSP module and the FPGA module through a dual-port RAM, the LCD display screen and the storage module are connected with the serial ports of the FPGA module, the FPGA module is connected with (two) RJ45 interfaces for input or/and output, and a clock channel of the RJ45 interfaces identifies the input or output of the RJ45 interfaces. The utility model ensures stable signal transmission of the whole system, reduces the cost, satisfies the application scene of most LCD display screens, does not need to be additionally provided with a switching power supply for supplying power, can reduce the failure rate of the LCD display screens and the receiving cards, and improves the running stability of the system.

Description

Liquid crystal display module control system based on high-speed singlechip

Technical Field

The utility model relates to the technical field of display screens, in particular to a liquid crystal display module control system based on a high-speed single chip microcomputer.

Background

In recent years, as the liquid crystal technology is mature, the liquid crystal display (LiquidCrystal Display, LCD) is widely used in the testing field, and many instruments currently adopt the liquid crystal display, so that the liquid crystal display is widely used in various graphic display systems.

The signal receiving card is a part of the control system of the LCD display screen and is responsible for converting the image data into a protocol of the LCD driving chip. Currently, a gigabit network chip is generally used to transmit data and a Synchronous Dynamic Random Access Memory (SDRAM) is used to buffer images, wherein the gigabit network chip is full duplex and can realize issuing of image data and readback of parameters.

The distance between the receiving cards in the existing use scene is usually less than three meters, and is far less than the furthest transmission distance of the gigabit network chip, so that the receiving cards are small in size and cost is increased intangibly.

Disclosure of Invention

The utility model aims to provide a liquid crystal display module control system based on a high-speed singlechip, which aims to solve the problems in the background technology.

In order to achieve the above purpose, the present utility model provides the following technical solutions:

the utility model provides a LCD module control system based on high-speed singlechip, includes DSP module, FPGA module, storage module, RJ45 interface and LCD display screen, establish data communication through two port RAMs between DSP module and the FPGA module, LCD display screen and storage module are connected with the FPGA module serial ports, the FPGA module is connected with (two) be used for input or/and the RJ45 interface of output, the input or the output of RJ45 interface is discerned to a clock channel of RJ45 interface.

Further, the clock signal output pin of the FPGA module is connected with the input end of the 3-8 line decoder, the RGB data output pin of the FPGA module is connected with the RGB data input end of the 245 three-state bus converter, the output end of the 3-8 line decoder is connected with the decoding signal input end of the 245 three-state bus converter, and the data output end of the 245 three-state bus converter is connected with the image data interface of the LCD display screen.

Furthermore, the FPGA module reads data of the storage module or stores the data into the storage module, and the storage module comprises SDRAM and FLASH.

Further, the system also comprises a power management module, wherein the power management module is used for supplying power to the system.

Further, the DSP module is based on an XC4VSX35 chip, the FPGA module is based on a TMS320C6416 chip, and the dual-port RAM is an IDT70V631S chip.

Compared with the prior art, the utility model has the beneficial effects that:

according to the utility model, the FPGA module can identify the input or output direction of the RJ45 interface through the clock channel, realizes the automatic switching of the transmission directions of the two paths of RJ45 interfaces, is convenient for the installation and debugging of the LCD display screen, is consistent with a receiving card based on the gigabit network chip, adopts the RJ45 interface as a data transmission interface between the receiving cards, omits two gigabit network chips on the traditional receiving card, can effectively reduce the cost of the receiving card, and simultaneously, the communication distance between the receiving cards can reach fifteen meters, no packet loss exists in one hour, ensures the stable signal transmission of the whole system, reduces the cost, and satisfies the application scenes of most LCD display screens.

The utility model relates to a clock signal output pin of an FPGA module, which is connected with an input end of a 3-8 wire decoder, an RGB data output pin of the FPGA module is connected with an RGB data input end of a 245 three-state bus converter, an output end of the 3-8 wire decoder is connected with a decoding signal input end of the 245 three-state bus converter, and a data output end of the 245 three-state bus converter is connected with an image data interface of an LCD display screen, so that RGB data and clock signals are output to the LCD display screen. The built-in power management module can supply power to the control circuit of the system and the interface of the LCD display screen (thereby supplying power to the LCD display screen), and a power supply switching power supply is not needed to be additionally arranged, so that the failure rate of the LCD display screen and the receiving card can be reduced, and the running stability of the system is improved.

Drawings

FIG. 1 is a block diagram of the system of the present utility model.

Fig. 2 is a schematic diagram of a specific connection between an FPGA module and an RJ45 interface according to the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In the description of the present utility model, it should be noted that the terms "upper end," "lower end," "inner," "outer," "front end," "rear end," "both ends," "one end," "the other end," and the like indicate an azimuth or a positional relationship based on that shown in the drawings, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "sleeved," "connected," and the like are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

Referring to fig. 1 to 2, the present utility model provides a technical solution:

the utility model provides a liquid crystal display module control system based on high-speed singlechip, includes DSP module, FPGA module, storage module, RJ45 interface and LCD display screen, its characterized in that, establish data communication through two mouthfuls of RAMs between DSP module and the FPGA module, LCD display screen and storage module are connected with the FPGA module serial ports, the FPGA module is connected with the RJ45 interface that is used for input or/and output, and the input or the output of RJ45 interface is discerned to a clock channel of RJ45 interface.

In the utility model, the rapid exchange of data between the FPGA module and the DSP module is usually realized through a dual-port RAM chip. By introducing the dual-port RAM, the data transmitted by the FPGA are stored, and then the DSP module reads from the dual-port RAM, so that the efficiency is improved. The FPGA module, the dual-port RAM module, the DSP module and the like are adopted to realize the data operation processing and control functions, so that the communication and processing capacity of the system is greatly enhanced, the instantaneity of the system is ensured, and the data reading and writing can be flexibly controlled in various modes. The DSP module can adopt an XC4VSX35 chip, the FPGA can adopt a TMS320C6416 chip, the dual-port RAM adopts an IDT70V631S chip, the data transmission speed is improved, and the LCD display screen is preferably YXM070TLW03. Of course, the DSP module and the FPGA module can also select other devices with the existing model according to the requirement, for example, the DSP selects ADSP-BF531 of ADI company, the FPGA selects Spartan-3A series of Xilinx company, and the like.

The utility model can convert the format of Chinese character, character and graphic data through an external upper computer, send the data to a DSP module, and write the received data into FLASH. When the display is performed, the DSP module reads the data in the FLASH, the data is transmitted to the FPGA module through the SPI interface and the dual-port RAM, the FPCA generates a control time sequence required by the LCD display screen and completes bus arbitration logic, and the control time sequence is transmitted to the LCD display screen for display after being processed by the FPGA module.

According to the utility model, the dual-port RAM is preferably an IDT71V3577 chip, so that the data processing speed of the FPGA module is improved, and the high-speed scanning of images and the simultaneous receiving of new data are realized.

The FPGA module comprises at least two RJ45 interfaces (belonging to voltage differential signal interfaces) for input or/and output, wherein one clock channel of each RJ45 interface is used for identifying the input or output of the RJ45 interface (low voltage differential signal), the two channels of RJ45 interfaces can reach the image transmission capacity of a gigabit network chip at 333Mbps, and 2×2× 333.333Mbps×8/10= 1066.66Mbps. The other channel is used as a parameter readback channel, meanwhile, the FPGA module can recognize the input or output direction of the RJ45 interface through the clock channel, so that the automatic switching of the transmission directions of the two RJ45 interfaces is realized, the LCD display screen is convenient to install and debug, the RJ45 interface is consistent with a receiving card based on a kilomega network chip, the RJ45 interface is used as a data transmission interface between the receiving cards, two kilomega network chips on the traditional receiving card are omitted, the cost of the receiving card can be effectively reduced, meanwhile, the communication distance between the receiving cards can reach fifteen meters, no packet is lost within one hour, the whole system is stable in signal transmission, the cost is reduced, and the application scene of most LCD display screens is met.

According to the utility model, as shown in fig. 2, the FPGA module is respectively in communication connection with the RJ45 interface through the serial-parallel unit and the parallel-serial unit. The signal sent to the parallel-to-serial unit by the serial-to-parallel unit is sequentially subjected to 10B8B coding/decoding and 8B10B coding/decoding, the bandwidth requirement of image data transmission is reduced by using a 1/2 image compression technology, the error rate is effectively reduced by 8B10B coding of the data, and meanwhile, the maximum communication distance of an RJ45 interface is improved. Meanwhile, the FPGA module further comprises a register, and the register is respectively connected with the two RJ45 interfaces in a communication mode through SWIRE signal ends. The serial-parallel unit is in communication with the register.

The utility model relates to a clock signal output pin of an FPGA module, which is connected with an input end of a 3-8 wire decoder, an RGB data output pin of the FPGA module is connected with an RGB data input end of a 245 three-state bus converter, an output end of the 3-8 wire decoder is connected with a decoding signal input end of the 245 three-state bus converter, and a data output end of the 245 three-state bus converter is connected with an image data interface of an LCD display screen, so that RGB data and clock signals are output to the LCD display screen. The built-in power management module can supply power to the control circuit of the system and the interface of the LCD display screen (so as to supply power to the LCD display screen), and a power supply switching power supply is not needed to be additionally arranged, so that the failure rate of the LCD display screen and the receiving card can be reduced, and the running stability is improved.

Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims (5)

1. The utility model provides a liquid crystal display module control system based on high-speed singlechip, includes DSP module, FPGA module, storage module, RJ45 interface and LCD display screen, its characterized in that, establish data communication through two mouthfuls of RAMs between DSP module and the FPGA module, LCD display screen and storage module are connected with the FPGA module serial ports, the FPGA module is connected with the RJ45 interface that is used for input or/and output, and the input or the output of RJ45 interface is discerned to a clock channel of RJ45 interface.

2. The control system of a liquid crystal display module based on a high-speed single chip microcomputer as set forth in claim 1, wherein the clock signal output pin of the FPGA module is connected to the input end of a 3-8 wire decoder, the RGB data output pin of the FPGA module is connected to the RGB data input end of a 245 three-state bus converter, the output end of the 3-8 wire decoder is connected to the decoding signal input end of the 245 three-state bus converter, and the data output end of the 245 three-state bus converter is connected to the image data interface of the LCD display.

3. The control system of a liquid crystal display module based on a high-speed single chip microcomputer as set forth in claim 1, wherein said FPGA module reads data from or stores data into a memory module, and said memory module includes SDRAM and FLASH.

4. The system of claim 1, further comprising a power management module, wherein the power management module is configured to supply power to the system.

5. The control system of a liquid crystal display module based on a high-speed single chip microcomputer as set forth in claim 1, wherein said DSP module is based on an XC4VSX35 chip, said FPGA module is based on a TMS320C6416 chip, and said dual-port RAM is an IDT70V631S chip.