CN219979135U - LCD display controller based on FPGA - Google Patents
LCD display controller based on FPGA Download PDFInfo
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- CN219979135U CN219979135U CN202321294983.5U CN202321294983U CN219979135U CN 219979135 U CN219979135 U CN 219979135U CN 202321294983 U CN202321294983 U CN 202321294983U CN 219979135 U CN219979135 U CN 219979135U
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Abstract
The utility model relates to the technical field of display controllers, in particular to an LCD display controller based on an FPGA, which comprises an FPGA module, a DSP module, a decoder and a decoding circuit, wherein data communication is established between the FPGA module and the DSP module through a dual-port RAM, the input end of the decoding circuit is connected with an I/O pin of the FPGA module, the output end of the decoding circuit is connected with an image data interface of an LCD display screen interface, the output end of the decoder is connected with the I/O pin of the FPGA module, and the decoding circuit is used for decoding DVI video input from the outside and then inputting the DVI video to the FPGA module for processing, and finally encoding the DVI video into an LVDS signal and outputting the LVDS signal to the image data interface of the LCD display screen interface. The utility model ensures stable signal transmission of the whole system, reduces the cost, satisfies the application scene of most LCD display screens, does not need to be additionally provided with a switching power supply for supplying power, can reduce the failure rate of the LCD display screens and improves the running stability of the system.
Description
Technical Field
The utility model relates to the technical field of display controllers, in particular to an LCD display controller based on an FPGA.
Background
In recent years, as the technology of liquid crystal is mature, liquid crystal display (LiquidCrystal Display, LCD) is increasingly used in the testing field, and many instruments currently adopt liquid crystal display, so that the liquid crystal display is widely used in various graphic display systems. Because the special liquid crystal display control module is adopted in the common LCD display, the complex graphic functions such as screen segmentation, screen logic operation and the like are realized. But this necessitates that the display module is controlled by the DSP and that its refresh frequency is limited. Some instruments (such as oscilloscopes) using LCD display have very high real-time requirements and high refresh rate requirements.
Disclosure of Invention
The utility model aims to provide an LCD display controller based on an FPGA, so as to solve the problems in the background technology.
In order to achieve the above purpose, the present utility model provides the following technical solutions:
the utility model provides a LCD display controller based on FPGA, includes FPGA module, DSP module, decoder and decoding circuit, establish data communication through two mouthfuls of RAMs between FPGA module and the DSP module, decoding circuit's input is connected with the I/O pin of FPGA module, decoding circuit's output termination LCD display screen interface's image data interface, the output of decoder is connected with the I/O pin of FPGA module for input the DVI video of external input is processed to the FPGA module after decoding, encodes into the image data interface that LVDS signal output to LCD display screen interface at last.
Further, the decoding circuit comprises a 3-8 line decoder and a 245 three-state bus converter, wherein a clock signal output pin of the FPGA module is connected with an input end of the 3-8 line decoder, an RGB data output pin of the FPGA module is connected with an RGB data input end of the 245 three-state bus converter, an output end of the 3-8 line decoder is connected with a decoding signal input end of the 245 three-state bus converter, and a data output end of the 245 three-state bus converter is connected with an image data interface of an interface of the LCD display screen.
Further, the power management module is connected to the power pins of the FPGA module, the DSP module and the power interface of the LCD display screen interface respectively.
Furthermore, an I/O pin of the FPGA module is connected with a memory module.
Further, the LCD display screen interface is used for being connected with an LCD display screen.
Further, the DSP module is based on an XC4VSX35 chip, the FPGA module is based on a TMS320C6416 chip, the dual-port RAM is an IDT70V631S chip, and the LCD display screen is based on YXM070TLW03.
Compared with the prior art, the utility model has the beneficial effects that:
the utility model solves the technical problems that the display module is controlled by the DSP at present and the refresh frequency is limited to a certain extent by fully utilizing the characteristics of high-speed computation of the DSP and parallel processing of the FPGA (industrial-grade chip), and can meet the requirements of high real-time performance of an instrument applying LCD display and relatively high refresh rate.
The utility model is an LCD display controller which fully utilizes the characteristics of high-speed computation of DSP and parallel processing of FPGA (industrial chip). The controller can receive 2 paths of DIV signals, and the FPGA generates LVDS signals required by a TCON (screen driving board) of the LCD display screen through video processing. And finally, connecting the display screen with an LCD display screen through an LCD display screen interface, and displaying the display screen.
The utility model relates to an FPGA module, which comprises an RGB data output pin connected with an RGB data input end of a 245 three-state bus converter, an output end of a 3-8 wire decoder connected with a decoding signal input end of the 245 three-state bus converter, and a data output end of the 245 three-state bus converter connected with an image data interface of an LCD display screen, thereby outputting RGB data and clock signals to the LCD display screen. Through built-in power management module, can supply power (thereby supply power for LCD display screen) to the interface of control circuit and LCD display screen of system, need not be equipped with the switching power supply of power supply in addition, can reduce LCD display screen fault rate, improve the stability of operation simultaneously.
Drawings
FIG. 1 is a block diagram of the system of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the present utility model, it should be noted that the terms "upper end," "lower end," "inner," "outer," "front end," "rear end," "both ends," "one end," "the other end," and the like indicate an azimuth or a positional relationship based on that shown in the drawings, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "sleeved," "connected," and the like are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, the present utility model provides a technical solution:
the utility model provides a LCD display controller based on FPGA, includes FPGA module, DSP module, decoder and decoding circuit, establish data communication through two mouthfuls of RAMs between FPGA module and the DSP module, decoding circuit's input is connected with the I/O pin of FPGA module, decoding circuit's output termination LCD display screen interface's image data interface, the output of decoder is connected with the I/O pin of FPGA module for input the DVI video of external input is processed to the FPGA module after decoding, encodes into the image data interface that LVDS signal output to LCD display screen interface at last.
The LCD display controller mainly comprises a decoder, a DIV decoder, preferably an ADV7612, a video signal detection unit, a video signal scaling processing unit, an OSD menu processing unit, a video Alpha superposition processing unit, a color conversion unit, an LED backlight control, a low-temperature heating control and an embedded detection unit and other functional modules. The DIV video input from the outside is decoded by the ADV7612 and then is input into a video detection unit, and after the validity is detected, the whole video stream is processed through a series of unit modules such as scaling, color transformation, alpha superposition, gray scale expansion and the like, and finally, the video stream is encoded into LVDS signals and output to an LCD. Except for the DIV decoder, other control parts are realized by adopting an FPGA (EP 3C55F780I 7N) of Altera company and an external memory DDR2 SDRAM. The FPGA uses Nioss II software as a center, and each functional module is organically combined to realize various specific functions.
In the utility model, the rapid exchange of data between the FPGA module and the DSP module is usually realized through a dual-port RAM chip. By introducing the dual-port RAM, the data transmitted by the FPGA are stored, and then the DSP module reads from the dual-port RAM, so that the efficiency is improved. The FPGA module, the dual-port RAM module, the DSP module and the like are adopted to realize the data operation processing and control functions, so that the communication and processing capacity of the controller system is greatly enhanced, the real-time performance of the system is ensured, and the data reading and writing can be flexibly controlled in various modes.
Besides the above-listed FPGA module and DSP module type, the DSP module in the utility model can also adopt an XC4VSX35 chip, the FPGA can also adopt a TMS320C6416 chip, the dual-port RAM adopts an IDT70V631S chip, the data transmission speed is improved, and the LCD display screen is based on YXM070TLW03. Other devices with the existing model can be selected according to the requirements, such as the FPGA adopts the Spartan-3A series of Xilinx company, and the DSP adopts the ADSP-BF531 of ADI company. The device of the utility model is not enumerated any more except the above models, only the existing hardware components are combined together to form a new technical scheme related to system construction, and the technical problem to be solved can be solved, while part of the components can realize the functions by relying on the running of computer software programs, the computer software running in each component related to the utility model belongs to known software, the improvement of the computer software programs running on the components is not needed, and only the existing hardware components meeting the requirements are purchased, combined and connected according to the system framework set forth in the utility model.
The utility model can convert the format of Chinese character, character and graphic data through an external upper computer, send the data to a DSP module, and write the received data into FLASH. When the display is performed, the DSP module reads the data in the FLASH, the data is transmitted to the FPGA module through the SPI interface and the dual-port RAM, the FPCA generates a control time sequence required by the LCD display screen and completes bus arbitration logic, and the control time sequence is transmitted to the LCD display screen for display after being processed by the FPGA module.
According to the utility model, the dual-port RAM is preferably an IDT71V3577 chip, so that the data processing speed of the FPGA module is improved, and the high-speed scanning of images and the simultaneous receiving of new data are realized.
The decoding circuit comprises a 3-8 line decoder and a 245 three-state bus converter, wherein a clock signal output pin of an FPGA module is connected with an input end of the 3-8 line decoder, an RGB data output pin of the FPGA module is connected with an RGB data input end of the 245 three-state bus converter, an output end of the 3-8 line decoder is connected with a decoding signal input end of the 245 three-state bus converter, and a data output end of the 245 three-state bus converter is connected with an image data interface of an LCD display screen, so that RGB data and clock signals are output to the LCD display screen. Through built-in power management module, can supply power (thereby supply power for LCD display screen) to the interface of control circuit and LCD display screen of system, need not be equipped with the switching power supply of power supply in addition, can reduce LCD display screen and this display control's fault rate, make entire system signal transmission stable, the cost reduction satisfies the application scenario of most LCD display screens, improves the stability of operation.
The LCD display of the utility model adopts an external hardware field programmable gate array (Field Programmable Gate Array, FPGA) to generate various display control time sequences required by the LCD. The display data is also read by directly reading from DDR2SDRAM (or from memory SARM) by generating an address counter by the FPGA. The LCD is displayed as a color display screen with a resolution of 800 x 480 or higher resolution.
According to the utility model, aiming at the requirements of special use occasions, the FPGA is added with functions of embedded detection, wide-range backlight control, low-temperature heating control, key, serial communication and the like.
The utility model is an LCD display controller which fully utilizes the characteristics of high-speed computation of DSP and parallel processing of FPGA (industrial chip). The controller can receive 2 paths of DIV signals (with complete OSD screen control function), and generates LVDS signals required by an LCD display screen TCON (screen driving board) through a series of video processing. And finally, connecting the display screen with an LCD display screen through an LCD display screen interface, and displaying the display screen.
The utility model solves the technical problems that the display module is controlled by the DSP at present and the refresh frequency is limited to a certain extent by fully utilizing the characteristics of high-speed computation of the DSP and parallel processing of the FPGA (industrial-grade chip), and can meet the requirements of high real-time performance of an instrument applying LCD display and relatively high refresh rate.
Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The LCD display controller based on the FPGA is characterized by comprising an FPGA module, a DSP module, a decoder and a decoding circuit, wherein data communication is established between the FPGA module and the DSP module through a dual-port RAM, the input end of the decoding circuit is connected with an I/O pin of the FPGA module, the output end of the decoding circuit is connected with an image data interface of an LCD display screen interface, the output end of the decoder is connected with the I/O pin of the FPGA module, and the decoding circuit is used for decoding an externally input DVI video and then inputting the DVI video to the FPGA module for processing, and finally encoding the DVI video into an LVDS signal and outputting the LVDS signal to the image data interface of the LCD display screen interface.
2. The FPGA-based LCD display controller of claim 1, wherein the decoding circuit comprises a 3-8 line decoder and a 245 three-state bus converter, wherein the clock signal output pins of the FPGA module are connected to the input terminals of the 3-8 line decoder, the RGB data output pins of the FPGA module are connected to the RGB data input terminals of the 245 three-state bus converter, the output terminals of the 3-8 line decoder are connected to the decoding signal input terminals of the 245 three-state bus converter, and the data output terminals of the 245 three-state bus converter are connected to the image data interface of the LCD display.
3. The FPGA-based LCD display controller of claim 1, further comprising a power management module connected to the power pins of the FPGA module, the DSP module, and the power interface of the LCD display screen interface, respectively.
4. The FPGA-based LCD display controller of claim 1, wherein the I/O pins of the FPGA module are connected to a memory module.
5. An FPGA-based LCD display controller as claimed in claim 1 wherein the LCD display screen interface is for interfacing with an LCD display screen.
6. The FPGA-based LCD display controller of claim 5, wherein the DSP module is based on an XC4VSX35 chip, the FPGA module is based on a TMS320C6416 chip, the dual port RAM is an IDT70V631S chip, and the LCD display screen is based on YXM070TLW03.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321294983.5U CN219979135U (en) | 2023-05-25 | 2023-05-25 | LCD display controller based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321294983.5U CN219979135U (en) | 2023-05-25 | 2023-05-25 | LCD display controller based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219979135U true CN219979135U (en) | 2023-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202321294983.5U Active CN219979135U (en) | 2023-05-25 | 2023-05-25 | LCD display controller based on FPGA |
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| CN (1) | CN219979135U (en) |
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- 2023-05-25 CN CN202321294983.5U patent/CN219979135U/en active Active
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