CN221081389U - Low-resolution video preview control platform based on MPSoC - Google Patents
Low-resolution video preview control platform based on MPSoC Download PDFInfo
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- CN221081389U CN221081389U CN202322742462.8U CN202322742462U CN221081389U CN 221081389 U CN221081389 U CN 221081389U CN 202322742462 U CN202322742462 U CN 202322742462U CN 221081389 U CN221081389 U CN 221081389U
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Abstract
The utility model discloses a low-resolution video preview control platform based on MPSoC, which belongs TO the technical field of image processing and display, and comprises a video signal input end, a PL module, a PS module and a display screen, wherein the PL module comprises a video preprocessing module, a FRAMEBUF _WR module and a NATIVE TO LVDS module; the PS module comprises a DDR memory module, a software rendering module, a channel 1 and a video interface controller module; the video interface controller module comprises a video buffer management module, a video rendering pipeline module and a video interface source controller module; the video rendering pipeline module is respectively connected with the video interface source controller module and the NATIVE TO LVDS module. The utility model overcomes the defect that the MPSoC platform in the prior art cannot display the low-resolution video, and provides an interface for the low-resolution screen, so that video signals are displayed on the low-resolution display screen and man-machine interaction is realized through the touch panel.
Description
Technical Field
The utility model relates to the technical field of image processing and displaying, in particular to a low-resolution video preview control platform based on MPSoC.
Background
MPSoC is a heterogeneous computing platform deduced by Xilinx based on a 16nm technology, and is widely used in the industry due to flexible and stable characteristics. However, the video displayed on the MPSoC platform can only be a high-definition video, and the main workflow is shown in a first diagram.
The HDMI interface conversion chip receives the HDMI video signal and converts the HDMI video signal into an MIPI video signal, 4K video coding and decoding and display control software is arranged in the Haishi image processing chip, the MIPI video signal is received and converted into a 4K HDMI video signal, and the 4K display screen receives and displays 4K HDMI video data of the Haishi image processing chip through the HDMI interface.
Chinese patent CN 110733444A, an ADAS driving assistance system based on the mpssoc platform, also describes converting image data into HDMI format through an image output module, where the HDMI interface is connected to a monitor through a cable, and the final image is displayed on the monitor.
The visual display of high-definition video is currently mainstream, but in real life, low-resolution video still exists because of the advantages of low occupied memory and the like, and the display of low-resolution video still exists. However, the existing MPSoC platform does not have an interface for the low resolution screen, so that the MPSoC platform cannot realize the preview of the low resolution video.
Disclosure of utility model
The utility model aims to solve the technical problem of designing a low-resolution video preview control platform based on MPSoC, wherein the platform is provided with an interface for a low-resolution screen, so that the preview of the low-resolution video is realized.
In order to solve the technical problems, the utility model adopts the following technical scheme: the low-resolution video preview control platform based on MPSoC comprises a video signal input end, a PL module, a PS module and a display screen, wherein the PL module comprises a video preprocessing module, a FRAMEBUF _WR module and a NATIVE TO LVDS module; the PS module comprises a DDR memory module, a software rendering module, a channel 1 and a video interface controller module; the video interface controller module comprises a video buffer management module, a video rendering pipeline module and a video interface source controller module; and the output end of the video rendering pipeline module is respectively connected with the video interface source controller module and the NATIVE TO LVDS module.
Further, the input end of the video preprocessing module is connected with the video signal input end, and the input end of the FRAMEBUF _WR module is connected with the output end of the video preprocessing module.
Further, the video signal input end is used for collecting video signals, and the video preprocessing module is used for processing the video signals and transmitting the video signals to the FRAMEBUF _WR module.
Further, an input end of the DDR memory module is connected with an output end of the FRAMEBUF _WR module, an input end of the software rendering module is connected with an output end of the DDR module, and an input end of the channel 1 is connected with an output end of the software rendering module.
Further, the software rendering module is configured to process the video data in the DDR memory module and transmit the processed video data to channel 1.
Further, the output end of the channel 1 is connected with the input end of the video buffer management module, and the output end of the video buffer management module is connected with the input end of the video rendering pipeline module.
Further, the PS module further comprises a PS system graphical interface module, and the output end of the PS system graphical interface module is connected with the input end of the video buffer management module.
Further, the PL module and the PS module are connected by an AXI high-speed bus.
Further, the display screen is a low resolution display screen.
Preferably, the display screen is a touch liquid crystal panel.
The beneficial effects are that: the application sets the video interface source controller module in the video interface controller module, and connects the output end of the video rendering pipeline module with the video interface source controller module and the NATIVE TO LVDS module respectively, so that when the display is not connected, the video data can be directly output TO the NATIVE TO LVDS module of the PL module, and the NATIVE TO LVDS module processes the video data TO obtain the video signal with low resolution, and the video signal is displayed on the low resolution display screen.
According to the characteristics of the video interface controller, the video interface driver is modified, so that signals output to the PL can be output when a high-definition display is not connected, meanwhile, an MPSoC (program-controlled interface) is adopted, an interface is reserved for a low-resolution screen, the defect that a MPSoC platform cannot display low-resolution video in the prior art is overcome, meanwhile, an operating system GUI (graphical user interface) graph is supported, a PS system graphical interface module is arranged, video signal preview and a graphical operation interface can be finally displayed on the low-resolution display screen, and man-machine interaction is realized through a touch panel.
Drawings
Fig. 1 is a schematic diagram of a high definition video display in the prior art.
Fig. 2 is a schematic diagram of a low-resolution video preview control platform based on MPSoC according to an embodiment of the utility model.
Fig. 3 is a schematic diagram of a low-resolution video preview control platform based on MPSoC according to a second embodiment of the utility model.
Detailed Description
The present utility model will be described in detail below with reference to examples and drawings for the purpose of enhancing the understanding of the present utility model, the examples being intended to illustrate the present utility model and not to limit the scope of the present utility model.
Example 1
As shown in fig. 2, a low resolution video preview control platform based on MPSoC includes a video signal input terminal, a PL module, a PS module and a display screen, wherein the PL module and the PS module are connected through an AXI high-speed bus, the PL module includes a video preprocessing module, a FRAMEBUF _wr module and a NATIVE TO LVDS module, the input terminal of the video preprocessing module is connected TO the video signal input terminal, receives external video signal data, and then performs preprocessing, such as scaling resolution TO a required resolution, then transmits the video signal data TO the input terminal of the FRAMEBUF _wr module, and further transmits the video signal data TO the input terminal of the DDR memory module of the PS module through the output terminal of the FRAMEBUF _wr module.
The PS module comprises a DDR memory module, a software rendering module, a channel 1 and a video interface controller module, wherein the input end of the software rendering module is connected with the output end of the DDR memory module, processes video data in the DDR memory module and transmits the video data to the input end of the channel 1 through the output end; the video signal data in the channel 1 passes through a video buffer management module in the video interface controller, then passes through a video rendering pipeline module, and finally is output TO a NATIVE TO LVDS module in the PL module, and after being processed by the NATIVE TO LVDS module, the LVDS signal data is output and finally displayed on a low resolution display screen. Video signals can be displayed on the final low resolution display screen, and man-machine interaction can be realized on the touch panel.
The video interface controller module also comprises a video interface source controller module which is used for directly outputting video data TO a NATIVE TO LVDS module of the PL module when the MPSoC platform is not connected with the high definition display.
Example two
As shown in fig. 3, a low resolution video preview control platform based on MPSoC includes a video signal input terminal, a PL module, a PS module and a display screen, wherein the PL module and the PS module are connected through an AXI high-speed bus, the PL module includes a video preprocessing module, a FRAMEBUF _wr module and a NATIVE TO LVDS module, the input terminal of the video preprocessing module is connected TO the video signal input terminal, receives external video signal data, and then performs preprocessing, such as scaling resolution TO a required resolution, then transmits the video signal data TO the input terminal of the FRAMEBUF _wr module, and further transmits the video signal data TO the input terminal of the DDR memory module of the PS module through the output terminal of the FRAMEBUF _wr module.
The PS module comprises a DDR memory module, a software rendering module, a channel 1, a PS system graphical interface module and a video interface controller module, wherein the input end of the software rendering module is connected with the output end of the DDR memory module, processes video data in the DDR memory module and transmits the video data to the input end of the channel 1 through the output end; the output ends of the channel 1 and the PS system graphical interface module are respectively connected with the input end of the video buffer management module in the video interface controller, at the moment, video signal data in the channel 1 and the graphical interface data in the PS system graphical interface module pass through the video buffer management module TO form 2 video streams TO the video rendering pipeline module, then pass through the video rendering pipeline module and finally output TO the NATIVE TO LVDS module in the PL module, the NATIVE TO LVDS module processes the NATIVE TO LVDS data and then outputs LVDS signal data, and the LVDS signal data is finally displayed on a low-resolution display screen. The video signal and the graphic interface can be simultaneously displayed on the final low-resolution display screen, and man-machine interaction can be realized on the touch panel.
The video interface controller module also comprises a video interface source controller module which is used for directly outputting video data TO a NATIVE TO LVDS module of the PL module when the MPSoC platform is not connected with the high definition display.
The embodiments of the present utility model are disclosed in the preferred embodiments, but not limited thereto, and those skilled in the art will readily appreciate from the foregoing embodiments that various extensions and modifications can be made without departing from the spirit of the present utility model.
Claims (7)
1. The low-resolution video preview control platform based on MPSoC comprises a video signal input end, a PL module, a PS module and a display screen, and is characterized in that the PL module comprises a video preprocessing module, a FRAMEBUF _WR module and a NATIVE TO LVDS module; the PS module comprises a DDR memory module, a software rendering module, a channel 1 and a video interface controller module; the video interface controller module comprises a video buffer management module, a video rendering pipeline module and a video interface source controller module; the video rendering pipeline module is respectively connected with the video interface source controller module and the NATIVE TO LVDS module.
2. The MPSoC-based low-resolution video preview control platform of claim 1, wherein the video signal input, the video pre-processing module, the FRAMEBUF _wr module, the DDR memory module, the software rendering module, and the channel 1 are connected in sequence.
3. The MPSoC-based low-resolution video preview control platform of claim 2, wherein the channel 1, the video buffer management module, the video rendering pipeline module are connected in sequence.
4. The MPSoC-based low-resolution video preview control platform of claim 3, wherein said PS module further comprises a PS system graphical interface module, said PS system graphical interface module being coupled to said video buffer management module.
5. The MPSoC-based low-resolution video preview control platform of claim 1, wherein said PL module and said PS module are connected by an AXI high speed bus.
6. The MPSoC-based low-resolution video preview control platform of claim 1, wherein the display screen is a low-resolution display screen.
7. The MPSoC-based low-resolution video preview control platform of claim 1, wherein the display screen is a touch liquid crystal panel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322742462.8U CN221081389U (en) | 2023-10-12 | 2023-10-12 | Low-resolution video preview control platform based on MPSoC |
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| CN202322742462.8U CN221081389U (en) | 2023-10-12 | 2023-10-12 | Low-resolution video preview control platform based on MPSoC |
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